JPH04235412A - Majority circuit - Google Patents

Abstract

PURPOSE:To provide the majority circuit with a simple circuit and to sufficiently apply the circuit to the high speed operations. CONSTITUTION:The load values for plural bits is preliminarily set in a shift register 13. This circuit is composed of a decision part 16 that the load values are shifted according to the enable information and the shift information and the majority decision is performed by the moving amount of the load value and a conversion part 15 provided with plural converters 10a to 10d obtaining the shift information deciding that the digital signals are inputted by 2 bits and that the load values are shifted to the left or right according to the number that the 2 bits are multiplied by 0.1 and the enable information deciding input enable in the shift register 13.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to majority voting circuits. Specifically, the present invention relates to a circuit that takes a majority vote among a plurality of outputs that have been error-corrected and output by a Viterbi decoder or the like.

0002

2. Description of the Related Art In devices that handle digital signals, such as receiving devices of wireless devices, a Viterbi decoder is sometimes used to restore encoded digital signals to their original state, that is, to decode them. When performing error correction, the Viterbi decoder converts one bit of the digital signal into 8 bits, for example.
It is expressed as a 0 or 1 candidate (8 bits) and output. Therefore, a majority vote is taken between the 0s and 1s output as 8 bits, and the one with the larger number is determined as the digital signal for 1 bit. A circuit used to take such a majority decision is a majority decision circuit.

FIG. 3 shows a block diagram of a conventional example. The 8 bits output from the Viterbi decoder (e.g. 1, 1,
1, 0, 0, 0, 0, 0) (as mentioned above, the 1-bit digital signal before error correction) is sent 2 bits at a time to 1-bit adders 1a, 1b, 1c, and 1d. 1,0 from adder 1a ("2" in decimal notation; hereinafter, decimal notation is indicated by ""), 0,1 ("1") from adder 16, adder 1c , 1d output 0 and 0 (“0”), respectively. Adders 1a, 1b
and the outputs of adders 1c and 1d are input to 2-bit adders 2a and 2b, respectively, and from adder 2a, 0, 1, 1
(“3”), and 0, 0, 0 (“0”) are output from the adder 2b, respectively.

[0004] The outputs of the adders 2a and 2b are input to a 3-bit adder 3, and the outputs from the adder 3 are 0, 0, 1, 1 ("3"
) is output and input to the comparator 4, where it is compared with the comparison value 0, 1, 0, 0 ("4"). In this case, since the output of the 3-bit adder 3 is smaller, the comparator 4 outputs 0.

FIG. 4 shows a block diagram of another conventional example. 8-bit digital signal from Viterbi decoder (1, 1,
1, 0, 0, 0, 0, 0) is converted into a serial signal by the parallel/serial converter 5, and is input as an enable signal to the counter 6 to count the number of 1s. 1,1 (“3”) is output. The output of the counter 6 is compared with the comparison value in the comparator 4.
outputs 0.

[0006]

[Problems to be Solved by the Invention] The conventional example shown in FIG.
Since the configuration uses many adders, the circuit scale becomes large and there is a problem that it cannot be configured at low cost.

The conventional example shown in FIG. 4 has a problem in that the read frequency of the parallel/serial converter 5 is eight times the read frequency of the Viterbi decoder, making it unsuitable for high-speed operation. SUMMARY OF THE INVENTION An object of the present invention is to provide a majority voting circuit that has a simple circuit configuration and is sufficiently applicable to high-speed operation.

[0008]

[Means for Solving the Problems] In the majority voting circuit according to the present invention, a load value of multiple bits is set in advance in a shift register, and the load value is shifted to the left or right according to enable information and shift information. , a determination unit that performs a majority decision based on whether or not a predetermined number of bits of the load value are 1 or 0; The converter includes a converter provided with a plurality of converters for obtaining shift information that determines to shift the load value to the left or right and enable information that determines input enable of the shift register.

[0009]

[Operation] In FIG. 1, when the two inputs of the converters 10a to 10d are 0, 1, or 1, 0, the enable information is 0, and the two inputs are 0, 0 because 0 and 1 are the same number. When , there are many 0s, so the shift information is 0 (left) and the enable information is 1. When the two inputs are 1 and 1, there are many 1s, so the shift information is 1 (right), and the enable information is converted to 1. do. The load value (for example, 0, 0, 0, 0, 1, 0, 0, 0) of the rotating shift register 13 is sequentially shifted by each enable information and shift information output of the converters 10a to 10d, and finally 0, 0, 0, 1, 0, 0, 0, 0. In the rotating shift register 13, a majority decision is made based on whether or not there is a 1 in the right 4-bit output, so in this case, 0 is determined.

For example, since the rotating shift register 13 is operated by simultaneously dividing an 8-bit input digital signal into two pieces of enable information and shift information, four clocks are required for each series of 8-bit information, that is, , the frequency for operating the shift register 13 should be four times the frequency of the input digital signal, and the readout frequency of the parallel/serial converter should be eight times the frequency of the input digital signal.
Compared to the conventional example, which required twice as much time, there is twice as much time, making it suitable for high-speed operation. Moreover, the circuit configuration can be simplified.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 10a to 10d are converters, which are composed of exclusive NOR gates and AND gates.
As shown in FIG. 2, the exclusive NOR gate outputs enable information and the AND gate outputs shift information for the two inputs (1) and (2). Shift registers 11 and 12 shift enable information and shift information output from the converters 10a to 10d, respectively. Converters 10a-10d
, shift registers 11 and 12 constitute a conversion section 15. 13 is a rotating shift register, for example 0
, 0, 0, 0, 1, 0, 0, 0 are set in advance, and the load values are shifted according to the outputs of the shift registers 11 and 12, and the output is obtained in the right four bits. Since the rotating shift register 13 makes a majority decision based on whether or not there is a 1 in its 4-bit output, the load value is set to 1 at one location, for example. Reference numeral 14 denotes a judgment circuit, which is composed of an OR gate and obtains a judgment result. The rotating shift register 13 and the determining circuit 14 constitute a determining section 16.

Now, if the output of the Viterbi decoder is 1, 1, 1, 0, 0, 0, 0, 0 as in the conventional example, then 1, 1 is output from the converter 10a, and 1, 1 is output from the converter 10b. 0,0,
1 and 0 are output from the converters 10c and 10d, respectively, and are sent to the shift register 11 as enable information and shift information.
, 12. In other words, when the inputs ■, ■ are 1, 0, or 0, 1, there are the same number of 0s and 1s, so the enable information is 0; when the inputs ■, ■ are 0, 0, there are many 0s, so the shift information is 0 (left) and the enable information is 1. When the inputs ■ and ■ are 1 and 1, there are many 1s, so the shift information is 1 (right) and the enable information is converted to 1.

First, the output of the converter 10d (enable information 1, shift information 0) is output from the shift registers 11 and 12, and as a result, the rotating shift register 13
The load value of is shifted left to 0, 0, 0, 1, 0, 0
,0,0. Next, the output of the converter 10c (enable information 1, shift information 0) is output from the shift registers 11 and 12, and thereby the load value of the rotating shift register 13 is further shifted to the left to 0, 0, 1. ，
It becomes 0, 0, 0, 0, 0. Next, shift register 1
From 1 and 12, the output of converter 10b (enable information 0
, shift information 0) are output, so that the load value of the rotating shift register 13 does not change. Furthermore, the output of the converter 10a (enable information 1, shift information 1) is output from the shift registers 11 and 12, and the load value of the rotating shift register 13 is thereby shifted to the right and becomes 0, 0, 0, 1. ,0,0,0,0.

The output of the rotating shift register 13 is 0.
. In this case, the output of the rotating shift register 13 is always outputted via the determination circuit 14, but the timing at which the shift is performed is determined by a pulse generator (not shown) based on the output of the converter 10a.
etc., and the output of the determination circuit 14 at this timing is adopted. This determines that the output of the Viterbi decoder is zero.

In the present invention, since the 8-bit output from the Viterbi decoder is simultaneously divided into two parts, enable information and shift information, and the rotating shift register 13 is operated, a series of 8-bit information is processed four times. In other words, the readout frequency of the shift registers 11 and 12 only needs to be four times the readout frequency of the Viterbi decoder. (requires 8 times the readout frequency)
It has twice the time margin compared to , and is suitable for higher-speed operation. Furthermore, the circuit configuration can be simplified and inexpensively compared to the conventional example shown in FIG.

[0016] In the above embodiment, the input digital signal is 8 bits, but this can be set as appropriate depending on the configuration of the Viterbi decoder, and the same operation as in the above case can be achieved even if the number is more or less than 8 bits. A majority vote will be taken.

Further, when the number of 0's and 1's in the input digital signal is the same, the output of the rotating shift register 13 is set to 1.

[0018]

According to the present invention, since majority voting processing is performed using two pieces of information, enable information and shift information, it is only necessary to operate with a clock having a frequency four times the frequency of the input digital signal. Compared to the conventional example that used a counter, it has more time and is suitable for higher-speed operation, and the circuit configuration is simpler and cheaper than the conventional example that uses adders in series. Can be configured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of a converter.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a block diagram of another conventional example.

[Explanation of symbols]

10a-10d converter 11, 12 Shift register 13 Rotating shift register 14 Judgment circuit 15 Conversion section 16 Judgment section

Claims (1)

[Claims] Claim 1: A plurality of bits of digital signal consisting of 0's and 1's are input in parallel, and in a majority decision circuit that determines the number of 0's and 1's in the input digital signal, a shift register (13) is provided with a plurality of bits in advance. A load value is set, the load value is shifted to the left or right according to enable information and shift information, and the majority decision is made based on whether a predetermined number of bits of the load value are 1 or 0. a determination unit (16) that receives the input digital signal 2 bits at a time and determines to shift the load value to the left or right according to the number of 0s and 1s in the 2 bits; A plurality of converters (
10a to 10d).