JPH1097410A - Mantissa normalizing circuit for floating-point number - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mantissa normalizing circuit which is fast and small in scale. SOLUTION: To normalize an 8-bit mantissa, a cascade connection of a 4-bit left shifter 11, a 2-bit left shifter 12, and a 1-bit left shifter 13 is adopted. The 4-bit left shifter 11 makes a 4-bit left shift when C2=1, the 2-bit left shifter 12 makes a 2-bit left shift when C1=1, and the 1-bit left shifter 13 makes a 1-bit left shift when C0=1 respectively. Then C2=1 is set when the most significant 4 bits of the 8 input bits representing the mantissa to be normalized are all '0'-value bits, C1=1 is set when the most significant 2 bits of 8 bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12 are both '0'-value bits, and C0=1 is set when the most significant bit of 8 bits supplied from the 2 bit left shifter 12 to the 1-bit left shifter 13 is a '0'-value bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a circuit for normalizing a mantissa of a floating-point number.

[0002]

2. Description of the Related Art In an information processing apparatus, a fixed-point number is converted into a normalized floating-point number, and a normalization process is performed on an operation result of two floating-point numbers.
Normalization of a floating point number means mantissa shift, that is, mantissa normalization, and adjustment of an exponent according to the mantissa shift, that is, exponent normalization.

Conventionally, a mantissa normalization circuit including a priority encoder and a plurality of left shifters has been known. Taking the normalization of an 8-bit mantissa as an example for the sake of simplicity, the priority encoder uses input 8-bits A7, A6,..., A1, A1 representing the mantissa to be normalized.
The number of consecutive 0-valued bits from the most significant bit A7 of 0 is detected, and three bits C2, C1, C0 constituting left shift amount data encoded to represent this number are supplied. The priority encoder sets the all-zero signal Z to 1 when all of the input 8 bits representing the mantissa are 0-valued bits, and resets the all-zero signal Z to 0 otherwise. When the most significant bit C2 of the left shift amount data supplied from the priority encoder is 1, the 4-bit left shifter shifts the input 8 bits representing the mantissa by 4 bits to the left and converts the 8 bits to 2 bits. The input 8 bits representing the mantissa are supplied as they are to the left shifter. When the next-order bit C1 of the left shift amount data supplied from the priority encoder is 1, the 2-bit left shifter shifts 8 bits supplied from the 4-bit left shifter left by 2 bits to obtain 8 bits. Is supplied to the 1-bit left shifter, and in other cases, the 8-bit supplied from the 4-bit left shifter is supplied to the 1-bit left shifter as it is. When the least significant bit C0 of the left shift amount data supplied from the priority encoder is 1, the 1-bit left shifter shifts 8 bits supplied from the 2-bit left shifter left by 1 bit to obtain 8 bits. In other cases, the 8 bits supplied from the 2-bit left shifter are output as they are. The eight bits B7, B6,..., B1, B0 of the 1-bit left shifter represent a normalized mantissa. That is, as long as there are bits having a value of 1 in the input 8 bits representing the mantissa,
The most significant bit B7 of the eight output bits always has the value 1. The three bits C2, C1, C0 constituting the left shift amount data supplied from the priority encoder
And the all-zero signal Z are provided to an exponential normalization circuit.

[0004]

In the conventional mantissa normalizing circuit as described above, after all bits constituting the shift amount data are determined by the priority encoder, the data is input to the input data representing the mantissa to be normalized. Since such a multi-stage shift process is started, the output of the final shift result is delayed. Further, since the internal configuration of the priority encoder is complicated, there is also a problem that the scale of the mantissa normalization circuit becomes large. The latter problem is caused by an increase in the number of transistors constituting the mantissa normalization circuit,
This causes an increase in layout area, an increase in the amount of wiring, an increase in power consumption, and the like.

An object of the present invention is to provide a high-speed and small-scale mantissa normalization circuit suitable for a semiconductor integrated circuit.

[0006]

In order to achieve the above object, the present invention determines a mantissa to be normalized while determining a plurality of bits constituting shift amount data from the most significant bit one by one. A configuration is adopted in which a plurality of stages of shift processing relating to input data are sequentially started. According to the present invention, the shift result of each stage is used for determining shift amount data. Then, since the shift processing of each stage starts earlier than all the bits constituting the shift amount data are determined, the normalization processing is performed at a higher speed than in the related art. In addition, since a priority encoder having a complicated internal configuration is not required, the scale of the mantissa normalization circuit is reduced.

When determining the most significant bit of the shift amount data, two candidates related to the next bit of the shift amount data are determined, and one of the two candidates is selected according to the determined most significant bit. By doing so, the speed of the normalization process is further increased.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a mantissa normalization circuit according to the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a mantissa normalizing circuit according to a first embodiment of the present invention. The circuit of FIG.
4-bit left shifter 11, 2-bit left shifter 12 and 1-bit left shifter 13 cascade-connected to each other, 4-input NO
R gate 21 and five inverters 22, 24, 25,
26 and 27, and a two-input NOR gate 23.

As shown in detail in FIG. 2, the 4-bit left shifter 11 includes eight selectors 15 for selecting one bit from two bits. Each selector 15 is composed of two CMOS transfer gates. In FIG. 2, E7, E6,..., E1, E0 represent 8 input bits, F7, F6,..., F1, F0 represent 8 output bits, and S4, XS4 represent 4-bit shift control signals. S4 and XS4 are signals complementary to each other. According to the configuration of FIG. 2, when S4 = 1 and XS4 = 0, F7 = E3, F6 = E2, F5 = E1, F4
= E0, F3 = 0, F2 = 0, F1 = 0 and F0 = 0. When S4 = 0 and XS4 = 1, F7
= E7, F6 = E6, F5 = E5, F4 = E4, F3 =
E3, F2 = E2, F1 = E1 and F0 = E0.
That is, when the 4-bit shift control signals S4 and XS4 are activated, the 4-bit left shifter 11 in FIG.
8 bits obtained by shifting the bits left by 4 bits are supplied,
In other cases, the input 8 bits are supplied as they are.

As shown in detail in FIG. 3, the 2-bit left shifter 12 includes eight selectors for selecting one bit from two bits. Each selector is
It is composed of two CMOS transfer gates. FIG.
, G1, G0 are input 8 bits, H7, H6,..., H1, H0 are output 8 bits,
2 and XS2 represent 2-bit shift control signals, respectively. S2 and XS2 are signals complementary to each other. According to the configuration of FIG. 3, when S2 = 1 and XS2 = 0, H7 = G5, H6 = G4, H5 = G3, H4 = G2.
, H3 = G1, H2 = G0, H1 = 0 and H0 = 0. If S2 = 0 and XS2 = 1, H7
= G7, H6 = G6, H5 = G5, H4 = G4, H3 =
G3, H2 = G2, H1 = G1 and H0 = G0.
That is, the 2-bit left shifter 12 in FIG. 3 inputs the input 8 when the 2-bit shift control signals S2 and XS2 are activated.
8 bits obtained by shifting the bits left by 2 bits are supplied,
In other cases, the input 8 bits are supplied as they are.

As shown in detail in FIG. 4, the 1-bit left shifter 13 is composed of eight selectors for selecting one bit from two bits. Each selector is
It is composed of two CMOS transfer gates. FIG.
, I1, I0 are input 8 bits, J7, J6,..., J1, J0 are output 8 bits,
1 and XS1 represent 1-bit shift control signals, respectively. S1 and XS1 are signals complementary to each other. According to the configuration of FIG. 4, when S1 = 1 and XS1 = 0, J7 = I6, J6 = I5, J5 = I4, J4 = I3.
, J3 = I2, J2 = I1, J1 = I0 and J0 = 0
Becomes When S1 = 0 and XS1 = 1, J
7 = I7, J6 = I6, J5 = I5, J4 = I4, J3
= I3, J2 = I2, J1 = I1 and J0 = I0. That is, the 1-bit left shifter 13 in FIG. 4 supplies the 8 bits obtained by shifting the input 8 bits to the left by 1 bit when the 1-bit shift control signals S1 and XS1 are activated. Are configured to supply the input 8 bits as they are.

In FIG. 1, A7, A6,..., A1, A
0 represents the input 8 bits representing the mantissa to be normalized. This input 8 bits is a 4-bit left shifter 11
Supplied to X7, X6,..., X1, X0 are 4
.., Y1 and Y0 represent the 8 bits supplied from the 2-bit left shifter 12 to the 1-bit left shifter B7 and B6. ,..., B1, B0 represent the output 8 bits supplied from the 1-bit left shifter 13 so as to represent the normalized mantissa. That is, as long as there are bits having a value of 1 in the input 8 bits representing the mantissa, the most significant bit B7 of the output 8 bits
Will always have the value 1. C2, C1, and C0 represent 3 bits constituting left shift amount data, and Z represents an all-zero signal.

If the most significant 4 bits A7, A6, A5 and A4 of the input 8 bits representing the mantissa to be normalized are all 0-valued bits, the 4-input NOR gate 21 outputs the left shift amount data. The most significant bit C2 is set to 1; otherwise, the most significant bit C2 is reset to 0. The most significant bit C2 becomes the 4-bit shift control signal S4 as it is, and is inverted by the inverter 22 to become 4 bits.
This becomes the bit shift control signal XS4. The 2-input NOR gate 23 outputs the most significant 2 bits X7, X of the 8 bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12.
If all 6 are 0-valued bits, the next bit C1 of the left shift amount data is set to 1; otherwise, the next bit C1 is reset to 0. The next-order bit C1
Becomes the 2-bit shift control signal S2 as it is, and is inverted by the inverter 24 to produce the 2-bit shift control signal X2.
S2. The inverter 25 includes the 2-bit left shifter 12
If the most significant bit Y7 of the eight bits supplied to the left shifter 13 is 0, the least significant bit C0 of the left shift amount data is set to 1, otherwise the least significant bit C0 is set to 1. Reset bit C0 to zero. The least significant bit C0 becomes the 1-bit shift control signal S1 as it is, and is inverted by the inverter 26 to become the 1-bit shift control signal XS1. The inverter 27 sets the all-zero signal Z to 1 when the most significant bit B7 of the eight output bits is a 0-value bit, and resets the all-zero signal Z to 0 otherwise.

According to the mantissa normalizing circuit shown in FIG. 1, first, it is determined whether or not all the four most significant bits A7, A6, A5 and A4 of the input eight bits representing the mantissa to be normalized are all 0-valued bits. Is checked by a four-input NOR gate 21. If the four bits A7, A6, A5, and A4 are all 0-valued bits, a left shift of at least 4 bits is necessary, so the most significant bit C2 of the left shift amount data is set to 1, and in other cases, Since no 4-bit left shift is required, the most significant bit C2 is set to 0. The 4-bit left shifter 11 outputs C2 = 1 (thus, S4 = 1 and XS4 =
In the case of (0), 8 bits obtained by shifting the input 8 bits representing the mantissa to be normalized by 4 bits to the left are supplied to the 2-bit left shifter 12, and C2 = 0 (therefore, S4 =
In the case of 0 and XS4 = 1), the input 8 bits are supplied to the 2-bit left shifter 12 as it is.

Next, whether the most significant two bits X7 and X6 of the eight bits supplied from the four-bit left shifter 11 to the two-bit left shifter 12 are 0-valued bits is determined by a two-input NOR gate 23. Can be examined. If both of the two bits X7 and X6 are zero-valued bits, at least two bits of left shift are necessary, so the next bit C1 of the left shift amount data is set to one, and in other cases, the two bits X1 and X6 are two bits. Since no left shift is required, the next-order bit C1 is set to 0.
It is said. The 2-bit left shifter 12 shifts 8 bits supplied from the 4-bit left shifter 11 by 2 bits leftward by 1 bit left when C1 = 1 (therefore, S2 = 1 and XS2 = 0). Supply to shifter 13 and C1
If = 0 (therefore, S2 = 0 and XS2 = 1), the 8 bits supplied from the 4-bit left shifter 11 are supplied to the 1-bit left shifter 11 as they are.

Finally, the inverter 25 determines whether the most significant bit Y7 of the eight bits supplied from the 2-bit left shifter 12 to the 1-bit left shifter 13 is a 0-value bit.
Investigated by If the most significant bit Y7 is a 0-valued bit, a one-bit left shift is required, so the least significant bit C0 of the left shift amount data is set to 1, otherwise, a one-bit left shift is required. Therefore, the least significant bit C0 is set to 0. The 1-bit left shifter 13 outputs C0
= 1 (therefore, S1 = 1 and XS1 = 0), an 8-bit obtained by shifting the 8-bit supplied from the 2-bit left shifter 12 by one bit to the left is output, and C0 = 0 (therefore, S1 = 0) If XS1 = 1), the 8 bits supplied from the 2-bit left shifter 12 are output as they are. The fact that the most significant bit B7 of the output 8 bits is a zero value bit means that the input 8 bits A7, A6,.
It means that all of A1 and A0 are zero value bits. Therefore, the most significant bit B7 is inverted by the inverter 27 to be an all-zero signal Z.

As described above, according to the present embodiment, the input 8 representing the mantissa to be normalized is determined while the three bits C2, C1, and C0 constituting the shift amount data are determined one by one from the most significant bit. Since the configuration in which the three-stage shift processing for bits is sequentially started is employed, the shift processing of each stage starts earlier than when all the bits constituting the shift amount data are determined. Therefore, the mantissa normalization processing is performed at a higher speed than in the related art. In addition, since a priority encoder having a complicated internal configuration is not required, the scale of the mantissa normalization circuit is reduced. Incidentally, the three bits C2, C1, C0 constituting the left shift amount data and the all-zero signal Z are supplied to an exponential normalization circuit (not shown).

(Embodiment 2) FIG. 5 is a diagram showing a mantissa normalizing circuit according to a second embodiment of the present invention. The circuit of FIG.
4-bit left shifter 11, 2-bit left shifter 12 and 1-bit left shifter 13 cascade-connected to each other, 4-input NO
R gate 31, first and second two-input NOR gates 3
2, 33 and six inverters 34, 36, 37, 3
8, 40, 41 and first and second selectors 35, 39
It is provided with. 4 bit left shifter 1
The internal configuration of each of the 1, 2-bit left shifter 12 and the 1-bit left shifter 13 is as shown in FIGS. Each of the first and second selectors 35 and 39 has two CMs.
It is composed of an OS transfer gate.

If the most significant four bits A7, A6, A5, and A4 of the eight input bits representing the mantissa to be normalized are all zero-valued bits, the four-input NOR gate 31 outputs the left shift amount data. The most significant bit C2 is set to 1; otherwise, the most significant bit C2 is reset to 0. The most significant bit C2 becomes the 4-bit shift control signal S4 as it is, and is inverted by the inverter 34 to become 4 bits.
This becomes the bit shift control signal XS4. First two-input NO
If the most significant two bits A7 and A6 of the input eight bits representing the mantissa to be normalized are both 0-valued bits, the R gate 32 outputs a candidate signal of the next bit C1 of the left shift amount data. That is, C1H is set to 1; otherwise, the candidate signal C1H is reset to 0. Second
The two-input NOR gate 33 outputs the left shift amount data when the most significant two bits A3 and A2 of the lower four bits of the input eight bits representing the mantissa to be normalized are all 0 value bits. The other candidate signal of the next-order bit C1, ie, C1L, is set to 1; otherwise, the candidate signal C1L is reset to 0. The first selector 35 outputs
When 2 = 0 (therefore, S4 = 0 and XS4 = 1), the candidate signal C1H is replaced by the candidate signal C1L when C2 = 1 (therefore, S4 = 1 and XS4 = 0). It is selected as the order bit C1. The next-order bit C1 is directly used as the 2-bit shift control signal S2.
And inverted by the inverter 38 to become the 2-bit shift control signal XS2. When the most significant bit X7 of the eight bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12 is a zero-valued bit, the inverter 36 is a candidate signal of the least significant bit C0 of the left shift amount data, that is, C0H. Is set to 1, otherwise the candidate signal C
Reset 0H to 0. When the most significant bit X5 of the lower 6 bits of the 8 bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12 is a 0-value bit, the inverter 37 outputs the least significant bit C0 of the left shift amount data.
The other candidate signal, ie, C0L, is set to 1; otherwise, the candidate signal C0L is reset to 0. The second selector 39 determines that C1 = 0 (thus S2 = 0 and XS
2 = 1) and the candidate signal C0H when C1 = 1 (thus S2 = 1 and XS2 = 0).
0L is selected as the least significant bit C0 of the left shift amount data. The least significant bit C0 becomes the 1-bit shift control signal S1 as it is, and is inverted by the inverter 40 to become the 1-bit shift control signal XS1. The inverter 41 sets the all-zero signal Z to 1 when the most significant bit B7 of the eight bits output from the 1-bit left shifter 13 is a 0-value bit, and sets the all-zero signal Z to 0 otherwise. It is to reset.

FIG. 6 shows a shift control operation of the mantissa normalizing circuit of FIG. First, the most significant 4 bits A7, A6, of the input 8 bits representing the mantissa to be normalized
It is 4-input N whether A5 and A4 are all 0 value bits.
It is checked by the OR gate 31. The four bits A7, A
When 6, A5 and A4 are all 0-valued bits, a left shift of at least 4 bits is necessary, so the most significant bit C2 of the left shift amount data is set to 1; , The most significant bit C2
Is set to 0. In parallel with this, the most significant 2 bits A7 of the input 8 bits representing the mantissa to be normalized
, A6 are both 0-valued bits by the first 2-input NOR gate 32, and the most significant 2 bits A3, A2 of the lower 4 bits of the input 8 bits are both 0-valued bits. It is checked by a second two-input NOR gate 33 whether or not each of them is present. 2 bits A7, A
6 are 0-valued bits, the candidate signal C1H is set to 1 since at least 2 bits of left shift is required when the 4-bit left shifter 11 does not perform shift processing, and 2 otherwise. Since no bit left shift is required, the candidate signal C1H is set to 0. 2 bits A3, A
If both 2 are 0-valued bits, the 4-bit left shifter 11 needs to shift at least 2 bits to the left when performing the shift processing, so that the candidate signal C1L is set to 1; Since the left shift of the bit is not required, the candidate signal C1L is set to 0. As described above,
Two candidate signals C1H, C1 related to the most significant bit C2 of the left shift amount data and the next bit C1 of the left shift amount data.
1L is determined (step 101).

The 4-bit left shifter 11 shifts the input 8 bits representing the mantissa to be normalized by 4 bits leftward by 4 bits when C2 = 1 (therefore, S4 = 1 and XS4 = 0). To the 2-bit left shifter 12,
When C2 = 0 (thus, S4 = 0 and XS4 = 1), the input 8 bits are supplied to the 2-bit left shifter 12 as it is. On the other hand, the first selector 35 selects the candidate signal C1H when C2 = 0 and the candidate signal C1L when C2 = 1 as the next bit C1 of the left shift amount data (steps 102 and 103). , 104).

Next, the inverter 36 determines whether or not the most significant bit X7 of the 8 bits supplied from the 4-bit left shifter 11 to the 2-bit left shifter 12 is a 0-value bit. It is checked by the inverter 37 whether or not the most significant bit X5 is a zero-value bit. If the bit X7 is a 0-value bit, the candidate signal C0H is set to 1 when the 2-bit left shifter 12 does not perform the shift processing, so that the candidate signal C0H is set to 1; Since no left shift is required, the candidate signal C0H is set to 0. If bit X5 is a 0 value bit, 2 bits left shifter 1
2 performs a shift process, a 1-bit left shift is required, so that the candidate signal C0L is set to 1. In other cases, the 1-bit left shift is not required.
0L is set to 0. As described above, the two candidate signals C0H, C0 related to the least significant bit C0 of the left shift amount data
0L is determined (step 105).

The 2-bit left shifter 12 shifts the 8-bit supplied from the 4-bit left shifter 11 by 2 bits to the left when C1 = 1 (therefore, S2 = 1 and XS2 = 0). 1 bit left shifter 13
When 1 = 0 (therefore, S2 = 0 and XS2 = 1), the 8 bits supplied from the 4-bit left shifter 11 are supplied to the 1-bit left shifter 11 as they are. On the other hand, when C1 = 0, the second selector 36 outputs the candidate signal C0H,
When C1 = 1, the candidate signal C0L is selected as the least significant bit C0 of the left shift amount data (steps 106, 107, 108).

Finally, the 1-bit left shifter 13 outputs C0 =
2 if 1 (hence S1 = 1 and XS1 = 0)
8 bits obtained by shifting the 8 bits supplied from the bit left shifter 12 to the left by one bit are output. When C0 = 0 (therefore, S1 = 0 and XS1 = 1), the 8 bits are supplied from the 2-bit left shifter 12. 8 bits are output as they are.
The most significant bit B7 of the eight output bits is inverted by the inverter 41 to be an all-zero signal Z (step 109).

As described above, according to this embodiment, the input 8 representing the mantissa to be normalized is determined while the three bits C2, C1, and C0 constituting the shift amount data are determined one by one from the most significant bit. Since the configuration in which the three-stage shift processing for bits is sequentially started is employed, the shift processing of each stage starts earlier than when all the bits constituting the shift amount data are determined. Therefore, the mantissa normalization processing is performed at a higher speed than in the related art. Moreover, the most significant bit C2 of the shift amount data and the two candidates related to the next bit C1 of the shift amount data are determined from the input 8 bits representing the mantissa to be normalized, and the determined most significant bit C2 is determined as the most significant bit C2. Depending on the choice of one of the two candidates,
From the 8 bits supplied from the bit left shifter 11 to the 2-bit left shifter 12, two candidates related to the least significant bit C0 of the shift amount data are determined, and one of the two candidates is selected according to the selected next bit C1. Is selected, so that the mantissa normalization process is further speeded up. Further, since a priority encoder having a complicated internal configuration is not required, the scale of the mantissa normalization circuit is reduced. It should be noted that three bits C2, C1, C0 constituting left shift amount data,
The all-zero signal Z is provided to an exponential normalization circuit (not shown).

In the first and second embodiments, the input data representing the mantissa to be normalized is composed of 8 bits, but the present invention is not limited to this number of bits. For example, in the case of a 16-bit mantissa, the number of input / output bits of each of the 4-bit left shifter 11, the 2-bit left shifter 12, and the 1-bit left shifter 13 in FIG.
And an 8-bit left shifter of 16-bit input / output, an 8-input NOR gate, and an inverter may be added to the preceding stage of the 4-bit left shifter 11. In the case of a 4-bit mantissa, the arrangement of the 4-bit left shifter 11, the 4-input NOR gate 21 and the inverter 22 in FIG.
In addition, the number of input / output bits of each of the 2-bit left shifter 12 and the 1-bit left shifter 13 may be changed to four. The mantissa normalization circuit in FIG. 5 can be easily changed.

The present invention is not limited to the multi-stage structure of the left shifter of the power of 2 bits. For example, 16
It is possible to adopt a two-stage structure of the left shifter for normalizing the bit mantissa. In this case, the left shifter of each stage
It is composed of 16 selectors for selecting one bit from four bits. Each selector is composed of, for example, four CMOS transfer gates. The first-stage left shifter implements 12-bit, 8-bit, 4-bit, and 0-bit left shifts, and the second-stage left shifter implements 3-bit, 2-bit, 1-bit, and 0-bit left shifts. Even with such a two-stage structure of the left shifter, an arbitrary amount of left shift from 15 bits to 0 bits can be realized. However, the logic gate configuration of the shift control circuit is changed according to the internal configuration of each left shifter.

In the first and second embodiments, the input mantissa is shifted leftward by an amount represented by the number of consecutive zero-valued bits from the most significant bit of the input mantissa. These embodiments can easily be modified to implement a left shift of an amount represented by the number of consecutive binary bits from the most significant bit of the input mantissa.

[0030]

As described above, according to the present invention, a plurality of bits constituting the shift amount data are determined bit by bit from the most significant bit thereof, and are converted into input data representing a mantissa to be normalized. Since a configuration for sequentially starting such multi-stage shift processing is employed, a high-speed and small-scale mantissa normalization circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a mantissa normalization circuit according to a first example of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a 4-bit left shifter in FIG.

FIG. 3 is a circuit diagram showing an internal configuration of a 2-bit left shifter in FIG. 1;

FIG. 4 is a circuit diagram showing an internal configuration of a 1-bit left shifter in FIG. 1;

FIG. 5 is a circuit diagram illustrating a configuration of a mantissa normalization circuit according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating a shift control operation of the mantissa normalization circuit of FIG. 5;

[Explanation of symbols]

 11 4-bit left shifter 12 2-bit left shifter 13 1-bit left shifter 15 selector 21 4-input NOR gate 22, 24 to 27 inverter 23 2-input NOR gate 31 4-input NOR gate 32, 33 2-input NOR gate 34, 36 to 38 , 40, 41 Inverters 35, 39 Selectors A7, A6, ..., A1, A0 Input data B7, B6, ..., B1, B0 Output data C2, C1, C0 Left shift amount data C1H, C1L, C0H, C0L Candidate signal S4 , XS4 4-bit shift control signal S2, XS2 2-bit shift control signal S1, XS1 1-bit shift control signal Z All-zero signal

Claims (2)

[Claims] 1. A circuit for normalizing a mantissa of a floating-point number, which is cascade-connected to each other and obtained by subjecting given data to a predetermined amount of shift processing according to a shift control signal. A multi-stage shifter configured to switch between an operation of supplying data to the next stage and an operation of directly supplying the given data to the next stage, and the plurality of input data representing a mantissa to be normalized. Means for supplying to the first-stage shifter of the stage shifters, and a shift control signal for the first-stage shifter is generated based on data supplied to the first-stage shifter, and each of the shifters after the first-stage shifter is provided with a shift control signal. Means for generating a shift control signal for each of the next-stage shifters based on data supplied to the next-stage shifter, wherein a mantissa normal number is calculated from a last-stage shifter of the plurality of shifters. Mantissa normalization circuit, wherein the result is to be obtained. 2. A circuit for normalizing a mantissa of a floating-point number, which is cascade-connected to each other and obtained by subjecting given data to a predetermined amount of shift processing according to a shift control signal. A multi-stage shifter configured to switch between an operation of supplying data to the next stage and an operation of directly supplying the given data to the next stage, and the plurality of input data representing a mantissa to be normalized. Means for supplying to the first-stage shifter of the stage shifters; means for generating a shift control signal for the first-stage shifter based on data supplied to the first-stage shifter; and based on data supplied to the first-stage shifter. To determine two candidates related to the shift control signal of the second-stage shifter, and determine the candidate related to the shift control signal of the second-stage shifter based on the generated shift control signal of the first-stage shifter. Means for selecting one of the two candidates, and a shift control signal for each next-stage shifter based on data supplied from each stage shifter after the first-stage shifter to each next-stage shifter. Two candidates for determining two candidates and selecting one of two candidates related to each shift control signal of the next next-stage shifter based on the determined shift control signal of each of the next-stage shifters. Means, wherein a mantissa normalization result is obtained from the last stage shifter of the plurality of stages of shifters.