JP2761558B2 - Bit search device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for normalization processing in floating point arithmetic, bit search instructions, detection of overflow of arithmetic shift, and the like. The present invention relates to a bit search device that searches for a bit position that appears for the first time.

2. Description of the Related Art As a device for executing a bit search for input data of 32 bits in one cycle, as shown in FIG.
A bit priority encoder is used. As shown in FIG. 4, the bit position N where the bit of logic "1" first appears when the input data is sequentially looked at the lower bit from the most significant bit MSB is set to 31 ₍₁₀₎ (decimal number _). (Display) is output with 5 bits of binary code.

In the bit search, in addition to the "1" bit search (FIG. 5A) for searching the bit position n where the logical "1" first appears when viewed from the most significant bit, as shown in FIG. A "0" bit search for searching for a bit position n where a logical "0" first appears when viewed from the most significant bit, and a logic S () for the most significant bit as viewed from the most significant bit as shown in FIG. 5C. S is "0"
Or "1") and the most significant inverted bit search for searching the bit position n where the inverted logic appears first. Further, for the three search methods shown in FIGS. 5A to 5C, the search result n is set to the most significant bit MSB of 1 as shown in FIG.
5 bits of binary code output as PBN as 0th in base 0 (positive logic output), and 5 bits of binary code NBN as 31st most significant bit MSB as 31st decimal as shown in FIG. 5E
(= ▲ ▼) to output (negative logic output).

Conventionally, input data and output data are subjected to software processing in accordance with the bit search method and output format, and therefore, several cycles of data shaping processing are required.

An object of the present invention is to provide a bit search device that can be executed in one cycle regardless of a bit search method and an output format.

According to the present invention, input data is output by the first logic circuit as positive logic data and negative logic data, and the most significant bits of the positive logic data and the negative logic data are stored in the first logic circuit. ,No. 2,
A third control signal is supplied to the multiplexer, and the second and third control signals or both the most significant bits are output from the multiplexer according to the state of the first control signal, and the positive logic data or the negative logic data is output according to the output. Logic data is selected by the data selector, and the selected data is supplied to the priority encoder, and the priority encoder outputs the input data as a binary number at a bit position that becomes logical "1" only when viewed from the most significant bit. Then, the output is output as a positive logic output and a negative logic output by the second logic circuit, and the positive logic output or the negative logic output is selectively output by the output selector according to the state of the fourth control signal.

FIG. 1 shows an embodiment of the present invention. The 32-bit input data [DB] is output by the first logic circuit 11 as positive logic data [DB] and negative logic data [▲ ▼]. The most significant bit DB00 of the positive logic data [DB] and the negative logic data [▲
The most significant bit ▲ ▼ of ▼) is a multiplexer
The signals are supplied to AND circuits 13 and 1 in 12, respectively. The first control signal IAL is supplied to both of the AND circuits 15 and 16 in the multiplexer 12.
1 is supplied, the second and third control signals IAL2 and IAL3 are supplied to the AND circuits 15 and 16, respectively, and the respective outputs of the AND circuits 15 and 16 are supplied to the OR circuits 17 and 18, respectively. AND circuit 13,14
Are supplied with inverted signals ▲ of the first control signal, and the outputs of the AND circuits 13 and 14 are respectively connected to the OR circuits 17 and 18.
Supplied to

Each output of the OR circuits 17 and 18 is supplied as an output of the multiplexer 12 to the data selector 19, and according to these outputs, positive logic data [DB] or negative logic data [▲ ▼] from the first logic circuit 11 is selected. You. The 32-bit data selected by the data selector 19 is supplied to a 32-bit priority encoder 22 through a path 21. Priority encoder
Numeral 22 outputs the bit position which first becomes logical "1" when viewed from the most significant bit of the input data as a 5-bit binary number. This output is supplied to the second logic circuit 23, and the positive logic output PBN and the negative logic output NBN are output from the second logic circuit 23 and supplied to the output selector 24. The output selector 24 is controlled by the fourth control signal IAL4,
When the control signal IAL4 is at logic L and the positive logic output PBN is selected, IAL
4 is logic H and the negative logic output NBN is selected.

In the above configuration, when the first control signal IAL1 is logic L, the AND circuits 13 and 14 are blocked, the AND circuits 15 and 16 are passed, and the second and third control signals IAL2 and IAL3 are OR circuits, respectively. Output from 17, 18 and the second control signal IAL2 is logic L
When the third control signal IAL3 is logic H, the data selector 19
, The negative logic data [▲ ▼] is selected, so that the priority encoder 22 has searched the input data [DB] for “0” bits. The second control signal IAL2 is logic H
When the third control signal IAL3 is logic L, the data selector 19
To select positive logic data [DB], and the priority encoder
At 22, it means that "1" bit search has been performed on the input data [DB].

On the other hand, if the first control signal IAL1 is logic H,
15 and 16 are blocked, the AND circuits 13 and 14 pass, and the inverted one of the most significant bits DB00 and ▲ ▼ of the positive logic data [DB] and the negative logic data [▲ ▼] is the OR circuit 17, Output from 18 and when OR00 is logic L, OR circuit 1
Outputs 7 and 18 become logic H and L, respectively.Positive logic data [DB] is selected by the data selector 19 and the most significant bit DB
00 is first searched by the priority encoder 22 for a bit position that becomes logical “1” with respect to logical L (“0”).
In the case of, the outputs of the OR circuits 17 and 18 become logic L and H, respectively, the negative logic data [▲ ▼] is selected by the data selector 19, and the most significant bit DB00 of the input data [DB] is logic H (“1”). This means that the priority encoder 22 first searches for a bit position that becomes logical “0” in response to “)”. That is, when the first control signal IAL1 is logic H, the input data [DB]
Is searched for the most significant inverted bit.

In this way, for the input data [DB], the “0” bit search, “1” bit search,
This is performed depending on the state of the second and third control signals IAL1, IAL2, IAL3,
The result is output from the priority encoder 22. This output is made into a positive logic output and a negative logic output by the second logic circuit 23. When the fourth control signal IAL4 is logic L, the positive logic output PBN
Is selected by the output selector 24, the negative logic output NBN is selected when IAL4 is logic H, and the search result output when the most significant bit is 0th and the search result output when the most significant bit is 31st And can be selectively obtained. First to first
FIG. 2 shows the relationship between the search method and the output format for each state of the fourth control signals IAL1 to IAL4.

If the input data [DB] cannot be searched with all bits “0” or all bits “1”, the priority encoder
Logic H is output from terminal 25 of 22 as overflow.

[Effects of the Invention] As described above, according to the present invention, the first to third control signals IAL1 are controlled by the first logic circuit 11, the multiplexer 12, and the data selector 19 using one priority encoder 22.
IAL 3 負 IAL IAL し 正 IAL に IAL の IAL し 正 正 正 〜 〜 〜 IAL IAL IAL IAL IAL IAL IAL IAL し 正 正 正. Alternatively, by outputting a negative logic output, various bit searches and various output formats can be performed in one cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a relationship between a control signal state, a bit search method and an output format, and FIG. 3 is a block diagram showing a conventional bit search device. FIG. 4 is a view showing the input data and output data, and FIG. 5 is a view showing various bit search methods and output formats.

Claims (1)

(57) [Claims] A first logic circuit for outputting input data as positive logic data and negative logic data; a most significant bit of each of the positive logic data and the negative logic data; a first, a second, and a third control signal; And a multiplexer that outputs the second or third control signal or both the most significant bits according to the state of the first control signal, and the positive logic data or the negative logic data according to the output of the multiplexer. The data selector to be selected and the output data of the data selector are supplied, and the bit position that becomes logical "1" only when viewed from the most significant bit is 2
A priority level encoder that outputs in radix, a second logic circuit that outputs the output of the priority encoder as a positive logic output and a negative logic output, and a positive logic of the second logic circuit according to the state of the fourth control signal. An output selector for selecting and outputting an output or a negative logic output.