JPH0363816A - Bit retriever - Google Patents

Abstract

PURPOSE:To attain bit retrieval and output in one cycle by outputting second and third control signals or the most significant bits of both signals corresponding to the state of a first control signal, selecting positive logic data or negative logic data corresponding to the output, and outputting the positive logic output and the negative logic output of an encoder with the priority order selectively. CONSTITUTION:The positive logic data or the negative logic data is supplied to the encoder 22 with the highest priority corresponding to the states of the first-third control signals IAL1-3 with a first logic circuit 11, a multiplexer 12, and a data selector 19. And the positive logic output or the negative logic output of the encoder 22 with the highest priority is outputted corresponding to a second logic circuit 23, an output selector 24, and a fourth control signal IAL4. In such a way, a various kinds of bit retrieval and a various kinds of output forms can be attained in one cycle.

Description

Detailed Description of the Invention "-Industrial Application Field" This invention is used for normalization processing in floating point arithmetic, bit search instructions, overflow detection in arithmetic shift, etc. The present invention relates to a bit search device that searches for a bit position where .

``Prior Art'' As a device that performs a bit search in 1 cycle for input data of 32 bits, there is a 3-bit search as shown in Fig. 3.
A 2-bin But-first encoder is used. As shown in Figure 4, this means that the input data is
Looking at the lower bits sequentially, we set the bit position n where the bit with logic "°l" appears for the first time, and the most significant bit position as 31.
+lo) Binary code 5 as (l O base number display) th
It is output in bits.

In addition to the "1" bit search (Figure 5A), which searches for the bit position n where logic "1" first appears from the most significant bit, there is also a bit search as shown in Figure 5B. ``0'' bit search, which searches for the bit position n where logic ``0'' first appears from the most significant bit, and logic S (of the most significant bit from the most significant bit) as shown in Figure 5 S
is "0" or "1") and the most significant inverted bit search which searches for the bit position n where the inverted logic S first appears. Furthermore, for these three search methods shown in Figure 5 A to C, the search result n is output as a binary code 5-bit PBN with the MSB as the 0th in the lO base as shown in Figure 5. (positive logic output), and as shown in Figure 5, the most significant bit MSB is set as the 31st decimal number and is output as a binary code of 5 bits NBN (=PBN) (negative logic output). .

In the past, input data and output data were processed by software according to these bit search methods and output formats, which required several cycles of data shaping processing.

An object of the present invention is to provide a bit search device that can be executed in one cycle regardless of the bit search method or output format.

"Means for Solving the Problem" According to the present invention, input data is outputted as positive logic data and negative logic data by the first logic circuit, and each of the most significant bits of these positive logic data and negative logic data and the first ．． Second
．． A third control signal is provided to the multiplexer, and a second . The third control signal or the upper bit of the rainfall amount is output from the multiplexer, the positive logic data or the negative logic data is selected by the data selector according to the output, and the selected data is supplied to the priority encoder, and the priority encoder The encoder looks at the input data from the most significant bit and outputs the bit position that becomes logic "1" for the first time as a binary number.The output is output as a positive logic output and a negative logic output by the second logic circuit, and the positive A logic output or a negative logic output is selectively outputted by the output selector according to the state of the fourth control signal.

Embodiment FIG. 1 shows an embodiment of the present invention, in which 32-bit input data (DB) is converted into positive logic data (DB) by the first logic circuit 11.
) and are output as negative logic data (DB). The most significant bit DBOO of the positive logic data (DB) and the most significant bit DBOO of the negative logic data (DB) are supplied to AND circuits 13 and 14 in the multiplexer 12, respectively.

A first control signal IALI is supplied to both AND circuits 15 and 16 in the multiplexer 12, and the AND circuit 15.1
6 and 2nd respectively. Third control signal IAL 2゜IAL
3 is supplied, and each output of AND circuits 15 and 16 is supplied to OR circuits 17 and 18, respectively.

The inverted signal IALL of the first control signal is supplied to both AND circuits 13 and 14, and each output of the AND circuits 13 and 14 is supplied to an OR circuit 17 and 18, respectively.

Each output of the OR circuits 17 and 18 is supplied to the data selector 19 as an output of the multiplexer 12, and positive logic data (DB) or negative logic data (DB) from the first logic circuit 11 is selected according to these outputs. . The 32-bit data selected by data selector 19 is supplied to 32-bit priority encoder 22 via bus 21. The priority echoer 22 looks at the input data from the most significant bit and outputs the bit position that first becomes logical "1" as a 5-bit binary number. This output is the second
The second logic circuit 23 outputs its positive logic output PBN and negative logic output NBN and supplies them to the output selector 24. The output selector 24 is controlled by a fourth control signal [AL4;
When TAL4 is logic high, the positive logic output PBN is selected, and when TAL4 is logic high, the negative logic output NBN is selected.

In the above configuration, when the 1111al signal IALI is logic 1, the AND circuit 13.14 is blocked, the AND circuit 15.16 is passed, and the second . Third control signal IAL2. IAL3 is output from the OR circuits 17 and 18, and when the second control signal IAL2 is logical and the third control signal IAL3 is logical H, the data selector 19 selects negative logic data (DB), and therefore the priority encoder In step 22, an "O" bit search is performed on the input data (DB). When the second control signal IAL2 is logical H and the third control signal IAL3 is logical, the data selector 19 selects positive logic data (DB), and the priority encoder 22 selects the "1" bit for the input data (DB). You will have performed a search.

On the other hand, when control signal IALI is logic H, AND circuits 15 and 16 are blocked, AND circuits 13 and 14 are passed, and positive logic data (DB) and negative logic data (DB)
The inverted values of Boo and DBOO are output from the OR circuit 17.18, and when DBOO is logical, the outputs of the OR circuit 17.18 become logical H and L, respectively, and the data selector 19, positive logic data (D
B) is selected and the topmost pin) DBOO is set to logic L (“0”).
”), the priority encoder 22 first searches for the bit position where the logic is “1”, and if DBOO is the logic H, each output of the OR circuit 17 and 18 is logic logic and becomes H, and the data selector 19 Negative logic data (DB) is selected in
This means that the priority encoder 22 searches for the bit position where OO becomes logic 0'' for logic H (l''). That is, when the first I11 control signal IALI is at logic H, the most significant inverted bit search is performed on the input data (DB).

In this way, "0" bit search, "1" bit search, and most significant inverted bit search for input data (DB) are performed.
1st. Second. Third control signal TALL.

IAL2. This is done based on the state of IAL3, and the result is output from the priority encoder 22. This output is the second
The logic circuit 23 outputs a positive logic output and a negative logic output. When the fourth control signal rAL4 is logic high, the output selector 24 selects the positive logic output PBN, and when IAL4 is logic high, the negative logic output NBN is selected. Thus, it is possible to selectively obtain a search result output when the most significant bit is the 0th bit and a search result output when the most significant bit is the 31st bit.

FIG. 2 shows the relationship between the search method and output format for each state of the first to fourth control signals IALI to IAL4.

Note that if the input data (DB) is all bits "0" or all bits "1" and the bit search cannot be performed, a logic H is output from the terminal 25 of the priority encoder 22 as an overflow.

"Effects of the Invention" As described above, according to the present invention, one priority encoder 22 is used to control the first to third control signals IALI to IAL3 by the tt* logic circuit 11, the multiplexer 12, and the data selector 19. The second logic circuit 23 and output selector 24 supply positive logic data or negative logic data to the priority encoder 22 according to the state of By outputting logical outputs, various bit searches and various output formats can be performed in one cycle.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the state of the control signal, the bit search method, and the output format, and FIG. 3 is a block diagram showing a conventional bit search device. , FIG. 4 is a diagram showing the input data and output data, and FIG. 5 is a diagram showing various bit search methods and output formats.

Claims (1)

[Claims] (1) A first logic circuit that outputs input data as positive logic data and negative logic data, and the most significant bits of these positive logic data and negative logic data, and first, second, and third control signals are inputted. The first
a multiplexer that outputs the second and third control signals or both of the most significant bits according to the state of the control signal; a data selector that selects the positive logic data or the negative logic data according to the output of the multiplexer; A priority encoder that is supplied with the output data of the data selector and outputs the bit position that becomes logic "1" for the first time from the most significant bit in binary, and outputs the output of the priority encoder as a positive logic output and a negative logic output. 1. A bit search device comprising: a second logic circuit that outputs a second logic circuit; and an output selector that selectively outputs a positive logic output or a negative logic output of the second logic circuit according to a state of a fourth control signal.