JPH0362622A - Circuit converting fixed decimal point data into floating decimal point data - Google Patents

Abstract

PURPOSE:To shorten the time required for the conversion even when number of bits of an inputted fixed point data is increased by providing a parallel/serial conversion parallel output circuit, a multiplexer circuit and a count-down circuit, etc. CONSTITUTION:The parallel/serial conversion parallel output circuit 1 loads an n-bit fixed point data (a), shifts up in the direction of the MSB and a multiplexer circuit 2 divides the n-bit parallel output of the circuit 1 in the unit of m-bit and outputs the result selectively. Moreover, a shift quantity detection circuit 3 receives an n-bit parallel output of the circuit 1, detects the shift and a priority encoder 4 receives the result of shift quantity detection from the circuit 3 and outputs a selection signal of the circuit 2. Then a count-down circuit 5 uses the result of shift quantity as an initial value to apply count down and the input data (a) is converted into a floating point data composed of m-bit normalized mantissa part output data (d) and an e-bit exponential part output data (f). That is, the number of times of shift-up and count-down is decreased to shorten the time required for the conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital logic circuits, and particularly to a circuit for converting fixed point data to floating point data.

[Conventional technology]

An example of a conventional circuit for converting fixed point data to floating point data is shown in FIG. 2 and will be described.

In Figure 2, the input fixed point data is n bits (n: any natural number), the output floating point data has a mantissa output of m bits (m: a number divisible by n bits), and an exponent output of e bits. The case of (e: any natural number) is shown.

In the figure, 21 is a parallel-serial conversion parallel output circuit, 22 is a countdown circuit, and 23 is a parallel-serial conversion parallel output circuit 21.
Mantissa output data MSB (Most 51gn
1ficant Bit) t and a load input signal q as inputs, 24 is an AND gate that receives the output of this OR gate 23 and a clock input signal p as inputs,
The output of the AND gate 24 is configured to be supplied to the clock terminal CLK of the parallel-to-serial conversion parallel output circuit 21 and the clock terminal CLK of the countdown circuit 22, respectively.

Next, the operation will be explained.

First, n-bit fixed-point data 0 is loaded in parallel to the parallel-to-serial conversion parallel output circuit 21 by the clock input signal p by setting the load input signal q to a load enable state.

Next, when the load input signal q is set to the load disable state, the parallel-to-serial conversion parallel output circuit 21 shifts up the n-bit fixed-point data 0 held as a shift register in the MSB direction according to the clock input signal p. It becomes possible to do so.

Here, one input of the OR gate 23 that determines whether or not to shift up is the mantissa output data MsB t, which is the parallel output of the parallel/serial conversion parallel output circuit 21 that outputs the m-bit mantissa output data r. Connected, MS
When B is a significant bit, the OR gate 23 and the AND gate 24 prohibit the cyclic clock output, and the upshift operation of the parallel-serial conversion parallel output circuit 21 is prohibited.

If MOB is not a significant bit, OR gate 2
3 and the AND gate 24 output, and the parallel/serial conversion/parallel output circuit 21 shifts up the held n-bit fixed point data 0 in the MSB direction. When the MSB of the parallel/serial conversion/parallel output circuit 21 becomes a significant bit, the clock output of the OR gate 23 and the AND gate 24 is prohibited, and the upshift operation of the parallel/serial conversion/parallel output circuit 21 is prohibited.

Also, the other input of the OR gate 23 is the load input signal q
, outputs a clock to the OR gate 23 and AND gate 24 at the time of loading, makes it possible to load n-bit fixed-point data 0 to the parallel-serial conversion parallel output circuit 21, and at the same time sets the initial value nm of the countdown circuit 22. do.

The countdown circuit 22 that outputs the m-bit exponent part output data field is operated by the same clock signal as the set diameter parallel-to-serial conversion parallel output circuit 21 of the initial value nm. 1
At the same time as the L parallel-to-serial conversion parallel output circuit 21 shifts up once, the countdown circuit 22 also counts down once. Then, the upshift operation of the parallel-to-serial conversion parallel output circuit 21 is prohibited! Since the countdown circuit 22 also counts down, the parallel-to-serial conversion parallel output circuit 2
The number of shifts up by 1 and the number of counts down by the countdown circuit 220 are not the same number.The input n-bit fixed point data 0 is converted into m-bit normalized mantissa output data r and m-bit exponent output data S. This means that it has been converted to floating point data.

[Problem to be solved by the invention]

In the conventional circuit for converting fixed-point data to floating-point data described above, when the parallel-serial conversion parallel output circuit operates as a shift register, the M of the parallel-serial conversion parallel output circuit is
Since the OB is shifted up in a case where it becomes a significant bit, there is a problem that as the number of bits of input fixed-point data increases, the time required for conversion increases.

[Means to solve the problem]

The circuit for converting fixed-point data into floating-point data of the present invention includes a parallel-to-serial conversion parallel output circuit that can load n-bit (n: any natural number) fixed-point data and shift it up in the MSB direction. A multiplexer circuit that divides the n-bit parallel output of the parallel-to-serial conversion parallel output circuit into units of m bits (m # a number divisible by n bits) and selectively outputs it, and the n-bit parallel output of the above-mentioned parallel-to-serial conversion parallel output circuit. A shift amount detection circuit receives the shift amount and detects the shift amount, a priority encoder receives the shift amount detection result from the shift amount detection circuit and outputs a selection signal for the multiplexer circuit, and the shift amount detection result is used as an initial value. It has a countdown circuit that counts down.

[Effect]

In the present invention, the parallel output of the parallel-to-serial conversion parallel output circuit that loads fixed-point data is divided into m-bit units, the shift amount is detected in m-bit units from the MSB, and an arbitrary m-bit area in which significant bits exist is detected. is selectively outputted to the multiplexer circuit, and at the same time, the initial value of the down counter is set to correspond to the shift amount in units of m bits. Further, the parallel/serial conversion/parallel output circuit is shifted up so that the MSB of the m-bit region selected by the multiplexer circuit becomes a significant bit, and at the same time, the down counter is counted down.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a circuit for converting fixed point data into floating point data according to the present invention.

In the figure, 1 is a parallel-to-serial conversion parallel output circuit that can load n-bit fixed-point data and shift it up in the MSB direction, and 2 is to convert the n-bit parallel output of this parallel-to-serial conversion parallel output circuit 1 into m bits. A multiplexer circuit that divides into units and selectively outputs it; 3 is a shift amount detection circuit that inputs the n-bit parallel output of the parallel-to-serial conversion parallel output circuit 1 and detects the shift amount; 4 is a shift amount detection circuit from this shift amount detection circuit 3 A priority encoder receives the amount detection result and outputs a selection signal for the multiplexer circuit 2. 5 is a countdown circuit that counts down using the shift amount detection result as an initial value. 6 is a clock input signal and the mantissa output data from the multiplexer circuit 2. This is an AND gate that takes MSBg as input.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

The n-bit fixed-point data a is the load input signal C.
The clock input signal is loaded in parallel to the parallel-to-serial conversion parallel output circuit 1 by setting the clock input signal to the load enable state.

Next, when the load input signal C is set to the load disable state, the parallel-to-serial conversion parallel output circuit 1 uses the clock signal k to shift up the held n-bit fixed-point data a in the MSB direction as a shift register. becomes possible.

Then, the shift amount detection circuit 3 divides and inputs the parallel output of the parallel-to-serial conversion parallel output circuit 1 into m-bit units.
The shift amount is detected from B in units of m bits, and the result is output to the priority encoder 4 as shift amount detection result output 1, and at the same time, the initial value of the countdown circuit 5 is set. Therefore, a value corresponding to the shift amount in units of m bits is set. is output as initial value data j.

The priority encoder 4 inputs the shift amount detection result output i of the shift amount detection circuit 3 and outputs a multiplexer select signal to the multiplexer circuit 2.

The multiplexer circuit 2 receives a multiplexer select signal and selects and outputs an arbitrary m-bit region in which a significant bit exists from among the parallel outputs t divided into 10 m-bit units of the parallel-serial conversion parallel output circuit.

The countdown circuit 5 sets the load input signal C to the load enable state and sets the clock input signal bV? h Initial (m data j is initialized. Next, load input signal C
When the clock input signal is placed in the load-disabled state, it is possible to start counting down from the initial setting value of the clock input signal.

According to the above-described operation, the present invention is configured such that after the 7'cn-bit fixed-point data a input to the parallel-serial conversion parallel output circuit 1 is loaded, the multiplexer circuit 2 outputs any of the parallel-serial conversion parallel output circuit 1. The m-bit region of is selected and output as the mantissa output data d, and the exponent output data f is output the same number of times as the parallel-to-serial conversion parallel output circuit 1 is shifted up so that the MSB becomes the significant bit. Since the countdown circuit 5 also counts down, the input n-bit fixed-point data a is converted into floating-point data of m-bit normalized mantissa output data d and e-bit exponent output data f. That means that.

〔Effect of the invention〕

As explained above, the present invention divides the parallel output of a parallel output circuit that loads fixed-point data into units of m bits, detects the amount of shift from the MSB in units of m bits, and detects the amount of shift in units of m bits from the MSB. At the same time, the initial value of the down counter is set to correspond to the shift (tTh) in units of m bits. Furthermore, by shifting up the parallel/serial conversion parallel output circuit so that the MSB of the m-bit region selected by the multiplexer circuit corresponds to the significant bit, and at the same time causing the countdown circuit to count down,
The number of upshifts of the parallel-to-serial conversion parallel output circuit and the number of downcounts of the down counter are less than m-1 times, and even if the number of bits of input fixed-point data increases, the time required for conversion can be shortened. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit for converting fixed point data to floating point data according to the present invention, and FIG.
The figure is a block diagram showing an example of a circuit for converting conventional fixed-point data into floating-point data. 1... Parallel-serial conversion parallel output circuit, 2... Multiplexer circuit, 3... Shift amount detection circuit, 4...
...Priority encoder, 5...Countdown circuit.

Claims (1)

[Claims] A parallel-to-serial conversion parallel output circuit that can load fixed-point data of n bits (n: any natural number) and shift up in the MSB direction, and a parallel output circuit for converting the n-bit parallel output of this parallel-to-serial conversion to m: a number divisible by n bits), and a multiplexer circuit that selects and outputs it; and a shift amount detection circuit that receives the n-bit parallel output of the parallel-to-serial conversion parallel output circuit and detects the shift amount;
A fixed point fixed point system comprising: a priority encoder that receives the shift amount detection result from the shift amount detection circuit and outputs a selection signal for the multiplexer circuit; and a countdown circuit that counts down the shift amount detection result using the shift amount detection result as an initial value. A circuit that converts data to floating point data.