JPS62135932A - Bit shifting device - Google Patents

Abstract

PURPOSE:To execute the shifting of a data series inputted continuously at the real time by shifting and renewing the data inputted to said shifting means based on the result to accumulate and calculate the number of the bit which the first shifting means shifts. CONSTITUTION:First, to a register 5, the first 16 bit bit input data D0-D15 are stored and to a register 2, the second - fourth 16 bit input data D16-D31,...D48-D63 are accommodated. At such a time, the second shifting circuit 3 outputs D16-D31. Next, only for the number S of shifting where a shifting generating circuit 6 generates, the first shifting circuit 4 shifts the output of the register 5 and the second shifting circuit and holds it at the register 5. A shifting control circuit 7 adds the present number S of the shifting to the previous accumulated number of the shifting, outputs the remaining number Z of the shifting and shifts the second shifting circuit 3 by Z only at the time of the next action. When a carry CRY is outputted, the output of a register circuit 2 is renewed for 16 bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit shift device, and particularly to a bit shift device that obtains in real time a series of n-bit data shifted by m bits from a series of continuously inputted n-bit data. Regarding.

[Prior Art] Conventionally, small-capacity bit shift circuits (for example, 4-bit shifter F350 manufactured by Fairchild Corporation in the United States) are known, but large-capacity i! ! ! There has not been a bit shift device that can obtain, in real time, a series of n-bit data shifted by m bits from a series of n-bit data that is subsequently input. Suppose we have a human device that waits for m bits to cue a large series of continuously input n-bit data, and then outputs a series of n-bit data separated by n bits. However, since the cueing time is not constant, it cannot meet real-time requirements.

[Problems to be Solved by the Invention] The present invention has been made against the background of the above-mentioned prior art, and its purpose is to solve a large amount of continuously input n-bit data with a simple configuration. An object of the present invention is to provide a bit shift device that obtains a sequence of n-bit data shifted by m bits from a sequence in real time.

Means for Solving the L Problem] As a means for solving this problem, for example, the bit shift device of the actual journey example shown in FIG. 1 [Details are shown in FIGS. Of the 16-bit data series Do-D 256 input as input, first DI6 to D31. D32~
Buffer means 2-1.21-2.2-3 for sequentially holding D47, D48 to D63, and first bit shift means 4.5 according to the shift number 5=SO-33 generated by the shift number generation circuit 6. Data bit B output by
LO-BL15 (initially Do-D15) and data bits BHO-BH output from the second bit shift means 3
15 by S bits in parallel, and a 4-bit (1B=2') that outputs the carry CRY of the addition result obtained by cumulatively adding the shift number S and the remainder shift number Z=ZO-23. ) cumulative calculation means 7-1.
7-2 and the first and second bit data D16 to D31 . A second bit shift means 3 that parallel-shifts D32 to D47 by Z bits, and a data bit D input to the second bit shift means 3 according to carry CRY=1 of the output of the accumulation calculation means.
I6-031. An input data updating means 7 is provided which updates D32 to D47 by 16 bits to become D32 to D47 and D48 to D63.

[Operation] In the configuration shown in FIG. 1, for example, a series of 16-bit data that is input continuously is set to
1. ..., and shifted by 18 bits to create a 16-bit data series D18-D33, D34-D49 .・・・
. . , the first 16-bit input data Do-D15 is stored in the register 5, and the first 16-bit input data Do-D15 is stored in the register 2-1.2-2.
2-3 is the 16-bit input data DI6 from 2nd to t54.
~D31, D32~D47. D48 to D63 are stored respectively.

- No.J, 4-focus cumulative addition means 7-1.7-2 initially outputs carry CRY=O and remainder shift number Z=0 as the addition p&ll result of adding up to the immediately preceding shift sand S. ing. Therefore, the second bit shifting means 3 shifts the second and third input data bits DI6 to D31 . D32-D47
is shifted in parallel by O bits, and the line BHO-BH
D16 to D31 are output to 15. That is, 16-bit data D16-D31 without deviation is provided with respect to 16-bit data BLO-BL15 (initially DO-D15) fed back to one input of the first shift circuit 4.

Next, the first bit shift means 4 shifts the 16-bit data DO~015 of the register 5 and the 16-bit data D16~D31 output from the second bit shift means 3 by 10 hits, for example, according to the programmed shift number 5=10. Parallel shift and hold DIO to D25 in register 5.

Next, the cumulative addition means 7-1, 7-2 cumulatively adds the current shift number lO to the previous cumulative shift number O, and adds r! Outputs the result carry CRY=0 and the remainder shift number Z=lO. That is, in preparation for the subsequent shift operation, the second shift circuit 3 is fed back to one input of the first shift circuit 4 (16).
Bit data BLO~BL15 (next is DIO~D25)
This is to make it possible to provide 16-bit data D26 to D41 without any deviation.

Furthermore, if carry CRY=1, the input data updating means 7 updates the data bits D16 to D31, D32 to D47 input to the second bit shifting means 3 by 16 hits, and updates the data bits D32 to D47, D48 to It is set as D63. In this way, the bit shift operation without deviation is repeated, and output shift data without deviation is sequentially formed.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a bit shift device according to an embodiment. In FIG. 0, 1 is a memory circuit;
For example, bit sequences of codes encoded and compressed into MH codes, MR codes, etc. are sequentially stored in units of 16 hits. Such storage means 1 can be realized by a RAM, a latch circuit, or the like. 2 is a register circuit consisting of a plurality of parallel 16-bit registers, and 16-bit data sequentially read from the memory circuit 1 is stored in the plurality of registers in sequence. 3.4 is the second and first shift circuit,
Each shift circuit performs a bit parallel shift of an arbitrary number of bits from 0 to 15 bits on 31 bits of parallel input data bits, and outputs 16 bits of shifted data. 5 is a 16-bit register that holds output data, 6 is a shift number generation circuit that generates, for example, a programmed shift number S, 7 is an accumulator 7-1, 7-2 that cumulatively adds the shift number S, and This is a shift control circuit that controls updating of 16-bit input data according to carry CRY.

Figures 2 to 3 (a) and (b) relate to the explanation of the basic operation of the shift circuit. Figure 2 is a circuit diagram of the shift circuit, and Figure 3 (a) is a diagram showing the operation of the shift circuit. IJj diagram, Figure 3 (
b) is an explanatory diagram showing the operation of 4-bit shifters 61-76. In FIG. 2, 100 is the upper 2 bits S2 . of the shift code consisting of 4 bits SO to S3. With S3 as input, a total of four alternative selection signals BO/~B3/
(However, / means negative logic NOT) When the 0 selection signal BO/, which is a decoder, is LOW, the shift block 101 is activated, and when the selection signal B1/ is LOW, it is shifted. energizes block 102 and selects signal B
When the selection signal B3/ is at the LOW level, the shift block 103 is activated, and when the selection signal B3/ is at the LOW level, the shift block 104 is activated. 101 to 104 are shift blocks 1. For example, in shift block 101, a common output activation signal BO/ and shift code bit 5O1S1 are given to four 4-bit shifters 61 to 64, and furthermore, 4-bit shifters 61 to 64 are provided with a common output activation signal BO/ and shift code bit 5O1S1. 64 output bits AO to A3. A4~A7°A8~A11. AI2~A1
The signals No. 5 form a total of 16 bits of parallel output bit data AO-A15. 61-76 are the same 4-bit shift chips (for example, F350 manufactured by Fairchild Corporation in the United States) constituting each shift block 101-104. For example, the operation of the 4-bit shifter 61 is shown in FIG.
), the parallel bit data input terminals I3 to I-3 have parallel input data () Do
-D6 is connected, and the shift data output terminal Y3~
Output data bit lines AO to A3 are connected to Yo. In the 4-bit shifter 61, when the LOW level of the selection signal BO/ is applied to the output activation terminal OE, the signal levels of the output terminals Y3 to yo are activated, and when the HIGH level of the selection signal BO/ is applied, In this state, the signal level of the output terminals Y3 to yo is at high impedance level Z. Pit shift control is performed by the lower two bits So and SL of the shift code applied to the shift control v4 terminals Sc and Sl. That is, in FIG. 3(b), when the contents of shift codes So and Sl are 0.0, the number of shifts is O, and the parallel input data leaflet) DO~
The contents of D3 appear as they are in output data bits AO to A3. Also, when the contents of the shift codes So and Sl are 1.0, the number of shifts is 1 and the parallel input data biller)
The contents of Di-04 are shifted by one and appear on output data bits AO-A3. Similarly, shift code S
When the contents of o and Sl are 1 and l, the number of shifts is 3, and the contents of parallel input data bits D3 to D6 are shifted by three and appear on output data bits AO-A3. Thus, in shift block 101, four 4-bit shifters 61-64 are responsible for each output portion. The bit shifter 61 is AO-A3, the bit shifter 62 is A4 to A7, the bit shifter 63 is A8 to All, and the bit shifter 64 is A
They are I2 to A15. The output bit lines of shift blocks 101-104 are wired-ORed (Wl, W2°W3), and any one of the activated shift blocks enables the signals of data bits AO-A15.

In the configuration shown in FIG. 2, the shift circuit effectively shifts the 31-bit parallel input data bits DO-D30 from 0 to 15 bits.

That is, when shifting from 0 to 3 bits, shift block 10 whose parallel input data bits are DO to D18 is used.
1 to enable its output AO-A15, 4 to 7
To shift up to bits, the shift block 102 whose parallel input data bits are D4-D22 is activated to enable its outputs AO-A15, and when to shift up to bits 8-11, the parallel input data bits are D8-D.
26, the shift block 103 is energized, and the output A of 7 is activated.
To enable 0-A15 and shift to 12 to 15 bits, energize the shift block 104 whose parallel input data bits are DI2 to D30 and shift its output AO-A.
Enable 15. This operation is shown in FIG. 3(a).

4(a), (b) to FIG. 8 relate to a detailed operation explanation of the bit shift device of the embodiment, FIG. 4(&), (b) is a circuit diagram of the pit shift device, and FIG. FIG. 2L is a diagram explaining the operation of the second shift circuit 3 corresponding to shift codes ZO to Z3, and FIG.
6(a) to 6(d) are diagrams explaining the operation transition of the bit shift device, and FIG. 7 is a diagram explaining the operation of the first shift circuit 4 corresponding to FIG. 8 is a timing chart showing the operation transition of each shift state.

As a result of the above, for example, a series of 16-bit data that is input continuously can be converted to DO-D15. D16 to D31,...
16-bit data series D obtained by shifting this by 18 bits
The case where 18 to D33, D34 to D49, . . . are obtained will be explained.

First, in state 1 of FIG. 6(a), D16 to 031 are read out to register 2-1, D32 to D47 are read out to register 2-2, and register 2-1 is read out. -3, 048 to D63 are read out. In this state, since the signal ARDY/ is O (LOW level), the gate circuits 2-4 and 2-7 are activated, and one data input ALO to the shift circuit 3 is activated.
~AL15 is DI6~D31, and the other data input AHO-AH15 to the shift circuit 3 is D32~D4.
It is 7. In this state, the programmed outputs SO to S3 of the shift number generation circuit 6 hold the shift number S=0, and the cumulative addition output 2O of the accumulator 7-1.7-2
-23 (output of register E) holds shift number Z=0.

In addition, the carry signal CRY of 4-bit full adder ADD
is also O. Also, the shift blocks selected in this state are 3-1 and 4-1, and the number of shifts Z=0, so the output BHO-BH15 of the shift circuit 3 is D16~
D31 and supplies the feedback output Do-D15 of the register 5 with data without deviation. Further, since the number of shifts S=0, the output BLO-BL15 of the shift circuit 4 (output of the register 5) is the data DO-D15 held in the immediately previous state (not shown).

In state 2, the programmed outputs SO to S3 of the shift number generation circuit 6 hold the shift number 5=10, and the outputs ZO to Z3 of the accumulator 7-1.7-2 hold the cumulative shift number z=0. is held. Therefore, state 2
Since shift blocks 3-1 and 4-3 are selected and the number of shifts Z=O, the output BHO of shift circuit 3 is
~BH15 is D16~D31, and the number of shifts is 5=
10, the outputs BLO to BL15 of the shift circuit 4 become D10 to D25.

In state 3, the programmed output 5o-S3 of the shift number generation circuit 6 holds the shift number S=8, and the output ZO-Z3 of the accumulator 7-1.7-2 holds O+1.
Due to the addition of 0, the shift number Z:10 is held. Therefore, in state 3, shift block 3-
3 and 4-3 are selected, and the shift number Z=10, the outputs BHO to BH15 of the shift circuit 3 are D26 to
D41 and supplies the feedback output DIO-D25 of the register 5 with data without deviation. Also, the number of shifts S=8
Therefore, the output BL・0−BL15 of the shift circuit 4 is D
It becomes I8-D33. This is the first output data DI8~
It is D33.

On the other hand, the 4-bit accumulator 7-1.7-2 cumulatively adds the current shift number 8 to the previous cumulative shift number 10, and outputs 1 as the carry signal CRY. The register controller 7-3 outputs a memory request signal to the storage circuit 1 based on the carry signal CRY of 1. The memory circuit 1 stores the next 16-bit data D64 to D64 in response to the memory request signal.
Read D79 and store it in register 2-1. Further, the register controller 7-3 changes the output level of ARDY/ to 0 by the carry signal CRY of 1 to BRD Y/cy.
) Switch to output level 0. As a result, the gate circuits to be activated next are 2-6 and 2-9, and the corresponding registers are 2-2 and 2-3. Therefore, one data input ALO to AL15 to the shift circuit 3 is D32 to D47.
and the other data input AHO to the shift circuit 3
-AH15 is D48 to D63.

In state 4, the programmed outputs SO to S3 of the shift number generation circuit 6 hold the shift number 5=14,
Output 20-' of 4-bit accumulator 7-1゜7-2
Z3 becomes 8 by outputting 1 to the carry signal CRY.
+10=1 out of 18 The remainder shift number Z=2 for the carry of Li6 is held. Therefore, in state 4, shift blocks 3-1 and 4-4 are selected, and since the number of shifts Z=2, the outputs BHO to BH15 of shift circuit 3 are transferred to register 2-2.
The outputs BLO to BL15 of the shift circuit 4 are D34 to D49, which are obtained by further shifting the outputs D32 to D47 by 2 bits, and since the number of shifts is 5 = 14, the outputs BLO to BL15 of the shift circuit 4 are D32 to D49.
Becomes 47.

On the other hand, the 4-bit accumulators 7-1 and 7-2 cumulatively add the number of shifts 5=14 to the cumulative number of shifts Z=2 so far, and output 1 to the carry signal CRY. The register controller 7-3 outputs a memory request signal to the storage circuit 1 based on the carry signal CRY of 1. The memory circuit 1 stores the next 16-bit data D8 in response to the memory request signal.
0-D95 is read and stored in register 2-2.

Also, cash register, meta. The controller 7-3 changes the output level of BRDY/ to CRDY by 1 of the carry signal CRY.
/ Switch to output level O. As a result, the gate circuits to be activated next are 2-8 and 2-5, and the corresponding registers are 2-3 and 2-1. Therefore, shift circuit 3
One data input ALO-AL15 is D48 to D6
3, and the other data input AH to the shift circuit 3
O to AH15 are D64 to D79.

Thereafter, the programmed output SO of the shift number generation circuit 6
~S3 is a state 4 shift number 5 = 14 followed by a state 5 shift number S = 2, repeating 14 and 2 alternately, a total of 16 consecutive bits (14 + 2) with no deviation after the first 18 bit shift This is because all you have to do is shift.

Here, the number of shifts 5-14 is ! In addition to the cumulative shift number Z = 2 before rf, the number I becomes 16 (programmed as 1).

In state 5, the programmed outputs SO to S3 of the shift number generation circuit 6 hold the shift number S=2, and the output ZO-Z3 of the accumulator 7-1.7-2 is 1.
Since the addition of 4+2 has been performed, the cumulative shift number Z-0 is held. Therefore, in state 5, shift blocks 3-1 and 4-1 are selected and the number of shifts is z20, so the output BHO-BH15 of shift circuit 3 is D4.
8 to D63, and since the number of shifts S=2, the output BLO-BL15 of the shift circuit 4 becomes D34 to D49. This is second output data D34 to D49.

In state 6, the programmed output 5o-33 of the shift number generation circuit 6 holds the shift number 5=14 again, and the outputs ZO to Z3 of the accumulators 7-1, 7-2 are added by O40. As a result, the cumulative number of shifts Z = 2
is held. Therefore, in state 6, shift blocks 3-1 and 4-4 are selected, and the number of shifts Z=2.
Therefore, the output BHO-BH15 of the shift circuit 3 is D5
0 to D65, and the feedback output of register 5 is 034 to D4.
9 is supplied with data without any deviation. Also, the number of shifts is 5
= 14, so the output of shift circuit 4 BLO~BL15
becomes D48 to D63.

On the other hand, the 4-bit accumulator 7-1.7-2 cumulatively adds the shift number 5=14 to the cumulative shift number Z=2 and outputs 1 as the carry signal CRY.

The register controller 7-3 receives 1 of the carry signal CRY.
A memory request signal is outputted to the storage circuit 1 by the above.

The memory circuit 1 reads out the next 16-bit data D96-D111 in response to the memory request signal and stores it in the register 2-3. Further, the register controller 7-3 changes the output level O of CRDY/ to A by the carry signal CRY of 1.
Cut the RDY/ output level to 0. As a result, the gate circuits to be activated next are 2-4 and 2-7, and the corresponding registers are 2-1 and 2-2. Therefore, one data input ALO to AL15 to the shift circuit 3 is D64.
~D79, and the other data input AHO-AH15 to the shift circuit 3 is D8OND95.

In state 7, the programmed output 5o-33 of the shift number generation circuit 6 holds the shift number S=2 again, and the outputs zO to Z3 of the accumulators 7-1.7-2 are 1.
Due to the addition of 4+2, the shift number Z-0 is held. Therefore, in state 7, shift block 3
-1 and 4-1 are selected and the shift number Z=0, so the output of shift circuit 3 BHO~B) (15 is I)6
4 to D79, and since the number of shifts S=2, the output BLO-BL15 of the shift circuit 4 becomes 050 to D65. This is the third output data D50 to D65.

Thereafter, states 8 and subsequent states are performed in the same manner, and the timing charts of the above-mentioned shift operations are as shown in FIGS. 7 and 8.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a bit shift device that can perform large-capacity parallel data shift of any number of bits with an hour wheel configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the bit shift device of the embodiment, Fig. 2 is a circuit diagram of the shift circuit, Fig. 3(a) is an explanatory diagram showing the operation of the shift circuit, and Fig. 3(b) is a 4-bit shifter. 4(a) and 4(b) are circuit diagrams of the bit shift device, and FIG. 5(a) is a diagram showing the operation of bit shifters 61 to 76.
FIG. 5(b) is a diagram explaining the operation of the first shift circuit 4 corresponding to shift codes SO to S3, and FIGS. 6(&) to (d) are diagrams explaining the operation of the first shift circuit 3. FIG. 7 is a timing chart showing the state of reading data from the memory circuit 1. FIG. 8 is a timing chart showing the operation transition of each shift state. In the figure, 1... memory circuit, 2... register circuit, 3.
4... Shift circuit, 5... Register, 6... Shift number generation circuit, 7... Shift control circuit. Patent applicant: Canon Corporation No. 6 BHO~B) (15 Figure (b) ALO, ALI5 Figure 6 (c) ALO-ALI5 BLO-BL153HO~
BH15 -1,-\-

Claims (2)

[Claims] (1) Buffer means for sequentially holding a series of n-bit data; first bit shift means for parallel-shifting the data bits output from the first and second bit shift means by S bits according to the number of shifts S; an N-bit (n=2^N) cumulative calculation means for cumulatively calculating the number of shifts S and outputting the overflow of the calculation result and the remaining number of shifts Z; and according to the remaining number of shifts Z output from the cumulative calculation means. a second bit shift means for parallel shifting the first and second n-bit data held by the buffer means by Z bits; and a second bit shift means for parallel shifting the first and second n-bit data held by the buffer means; It is equipped with an input data updating means for updating the data series by n bits, and it is possible to update the data series by n bits.
A bit shift device characterized in that it obtains a bit-shifted series of n-bit data. (2) The bit shift device according to claim 1, wherein the cumulative calculation means cumulatively adds the shift number S and outputs a carry and a remainder shift number Z as a result of the addition.