JPS584449A - Instruction buffer control system - Google Patents

Abstract

PURPOSE:To reduce the number of registers which store the pre-fetched instruction groups, by selecting one unit out of a gathering comprising a current register, a target register and an instruction buffer register and then feeding an instruction to a pipeline control part. CONSTITUTION:A current register 11 loads the instruction word data read out of a storage part. A target register 10 loads the instruction word data read out of a main storage part. A selector 14 selects a unit out of a gathering comprising the register 11 and the register 10. The contents of the register selected by the selector 14 is loaded to an instruction buffer register 12. A selector 15 selects a unit out of the group comprising the registers 11, 10 and 12, and the instruction of the selected register is fed to a pipeline control part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an instruction packer control system that preempts instructions upon successful branching and stores them in a register.
This invention relates to an instruction buffer 7 control method that reduces the number of registers and determines the arrangement of registers and selectors so as not to degrade performance.

FIG. 1 shows a conventional instruction buffer control system, in which 1-0 to 1-3 are instruction buffer registers, 2
0 indicates the selector and 3Fi pipeline control unit, respectively. 0 Instruction buffer register 1-0.1-1.1-2.1-
3 each has an 8-byte structure.0 The length of the instruction word varies depending on the type of instruction and is 2 bytes, 4 bytes, or 6 bytes. Therefore, if the instruction word is 2 bytes long, s1 instruction registers can store four instruction words. A group of 8-byte instructions sent from the storage unit is stored in the instruction buffer.
Register 1 - 0.1 - 1.1 - 2.1 - O selected instruction buffer in BO 0 stored in register i - < ((xO, 1, 2 or 3) consists of a storage unit (storage control unit: S unit), an instruction control unit (I:L unit), and an arithmetic processing unit (E unit).Figure 1 shows a part of the instruction control unit. O First, the 98-byte instruction group is read from the storage device and stored in the instruction buffer registers 1-0 via the storage unit.Then, the next instruction is read out and stored in the instruction buffer register. 1-IKEI- is loaded, and after that, the instruction buffer register 1-0. is selected and input to the pipeline control unit 3 ◎ At this time, the instruction group in group A is called the current instruction 0 branch instruction pipe When executed 1
Branch destination instructions (referred to as target instructions) are loaded into the instruction pad register fi1-2.1-3 of 18 groups, and according to one branch prediction, either the current or target instruction is selected and pipe twinned. Input to the control unit 3. If the branch is successful, the instruction buffer registers 1-2 of group 8
．． 1-3 is used as the current instruction, and then an instruction is selected from the 8 groups, inputted to the pipeline control unit 31, and executed.

On subsequent instruction reads, the instruction word is loaded into eight groups of instruction buffer registers 1-2.1-3. If the branch is unsuccessful, the B-rated instruction buffer r-register 1-2.1-
Target instructions #3 in group A are collected, and the current instruction is subsequently selected and executed from the instruction buffer register 1-0.1-1 of group A. Thereafter, a group of instructions is loaded into the instruction buffer register of group A and input to the pipe twin control unit 3. 8 groups of instruction buffer registers 1-2.1-3
When executing one branch instruction using , load the A group instruction buffer register 1-0°1-IK branch destination instruction.

In the conventional instruction buffer control method as shown in FIG.
The instruction buffer register becomes idle. Furthermore, if one branch is unsuccessful when four instructions are loaded into the instruction buffer registers of the 8th group, the contents of the two instruction buffer registers of the 8th group are discarded. As described above, the conventional instruction buffer control method shown in FIG. 1 has the disadvantage that the instruction buffer register cannot be used effectively and there is a high probability of reading a branch destination instruction in vain. This eliminates the above drawbacks.

It is an object of the present invention to provide an instruction buffer control system which can reduce the number of registers for storing a group of instructions compared to the conventional instruction buffer control system without deteriorating performance. Therefore, 1) the instruction buffer control method of the present invention has a ninth current register for loading the instruction word data read from the storage section, and a ninth current register for loading the instruction word data t' read from the main storage section. a first selection means for selecting one from a set consisting of a target register, the current register and the target register; an instruction buffer into which the contents of the register selected by the first selection means are loaded;
and one from the set consisting of the current register, target register, and instruction parameter register.
and a second selection means for selecting the instruction in the selected register and supplying the instruction in the selected register to the pipeline control unit.
The present invention will be explained with reference to the drawings. Figure 2 is a block diagram of one embodiment of the instruction buffer control method of the present invention, and Figure 3 is a timetable for explaining its operation. Chart 〇 In Figure 2, 1G is the target instruction word register,
11 is an instruction word register, 12 is an instruction buffer register, 13 is a pipeline control section, and 14 and 15 are selectors, respectively.

The target instruction register 1G, instruction register 11, and instruction buffer register have an 8-byte configuration, the target instruction register IOK stores the target instruction, the instruction register 11 trap stores the current instruction, and the instruction buffer register IOK stores the target instruction.・Register 12 is sent from the 0 storage unit where the contents of target instruction word register/10 or instruction word register 11 are stored.
Byte instruction group tWhether to store in the target instruction word register lo or in the instruction word race/11o is determined by the write control signal from the pipeline control unit 13.The pipeline control unit 13 uses the conventional pipe twin In addition to the functions provided by the control IIO, there are functions for controlling the target instruction register Rot, a function for controlling the instruction register 11, a function for controlling the instruction buffer register 12t,
The 0 selector 14, which has a function of controlling the selector 14 and a function of controlling the selector 15 pipe, selects either the target instruction word register 1G or the instruction word register ti o P5o according to the control signal from the pipe twin control section 13. One is selected and the contents of the selected register are sent to the instruction buffer register 12tC. The selector 15 selects any one of the target instruction register 1G, the instruction register 11, or the instruction buffer e register 12 according to the control signal of the pipe twin control unit 13, and selects one of the nine registers. Sends the instruction to the pipeline control [113].

Normally, the read instructions are stored as 0 and 1 in the instruction register 11Ka through the storage unit.
When the next instruction is read, the contents of the instruction register 11 are shifted to the instruction buffer register 12, and the read instruction group is transferred to the instruction register 11 and the instruction buffer register 11 again. - Executed from register ■ ◎ When executing branch instruction tgA line: Fi,
The branch destination instruction is read and written to the target instruction word register 12.

By doing K in this way, you can temporarily hold the current instruction string and the target instruction string in the buffer register, so you can select and process either one as necessary.If the 0 branch is successful, the instruction word register The contents of 11 are cleared, and when the next instruction is read, they are shifted from the target instruction register lo to the instruction buffer register n, and a new data pipe instruction register 11fCI-1 is read.
Return to normal operation. If the branch is unsuccessful, the content of the target instruction word register 1O is only changed to the phoneme, which is fine for normal operation. ◎ FIG. 3 is a time chart showing a detailed explanation of the present invention. In the SS, ( is the address calculation cycle for instruction fetch, B1 and B2 are the instruction read cycle,
D is the instruction decoding cycle, Rh is the reading cycle of general-purpose registers such as index register and base register, A is the address calculation cycle of the operand, S El
and El indicate an execution cycle, CK a result check cycle, and W a write cycle to registers, etc. @When instruction A is incorporated into the pipeline control unit 13, the instruction word register 11 and instruction buffer・Register 1
The state of 2 changes to a state where instructions can be read from the main memory.6
Then, the 0 instruction B, which is read out at instruction 74- and is stored in the instruction word register IIK at %Dnicle, is taken into the pipeline control unit 13 two cycles later than the instruction, but the instruction When B is fetched and the own instruction readout state KTo is reached, reading out of the instruction is started. Command B
Since the instruction was read at step 70-, the contents of the instruction word register 11 are transferred to the instruction buffer register 12 in the flow OR cycle of instruction A. In the 70-D cycle of instruction B, the consecutively issued instructions are stored in the instruction word register 11. Two cycles later than the flow of instruction B, the next instruction is entered into the pipeline control unit 13KMIN.0 This instruction reads the target instruction from the instruction word register in the instruction register.

The 9 target instructions read out are stored in the target instruction word register IOK in the D cycle of this flow, but in the 74-OA cycle of the branch instruction, the instruction C is stored in the instruction buffer.
It is taken out from the register 12 and input to the pipe twin control unit 13, and its execution is started. Branch instruction flow A
If the establishment of the branch condition is predicted during the cycle, the branch destination instruction A in the target instruction word register IO is transferred to the pipe twin control 11 at the start of the 70th to 81st cycles of the branch instruction.
At 70-Et of the branch instruction, the read instructions are stored in the instruction word register 11tC and read out as the target instruction. When the contents of word register l0IIE) are moved to instruction buffer register uK, the branch target instruction B is transferred to selector 15 in target instruction word register lO.
As is clear from the above description, according to the present invention, it is possible to reduce the number of registers that store instructions that are executed first without deteriorating performance. However, in the above-described OII embodiment, there may be one instruction register, one instruction buffer register, and one target instruction register, or a plurality of each may exist. Also 1
When reading a normal instruction, the current instruction group tvx- may be written not only to the instruction register but also to the target instruction register.Furthermore, the roles of the instruction register and the target side register can be branched as in the conventional example. May be alternated with success.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional instruction buffer control method. FIG. 2 is a program diagram of one embodiment of the actual instruction buffer control method, and FIG. 3 is a time chart illustrating its operation. lO...Target instruction word register, 11-...Instruction word register xp*L1-...Instruction buffer register %13
... Pipe twin control section, 14 and 15 ... Seven Shikta Patent applicant: Fujitsu Ltd. Kinsha, Shioiri Bentsugi, Kyotani Yobu

Claims (1)

[Claims] a current register for reading instruction word data tvx- from the storage section, a target register for reading instruction word data tI2- read from the main storage section, a set consisting of the current register and the target register; A first selection means for selecting one from among the registers;
A second register is selected from a set consisting of the instruction buffer to be loaded, the current register, the target register, and the instruction buffer register, and supplies the selected register to the instruction pipeline control unit. Instruction buffer control method with selection means