SE510295C2 - Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method - Google Patents

Abstract

The present invention relates to a method of handling conditional jump instructions in a computer processor (1). Space is allocated in a so-called instruction buffer (3) for respective instructions read into the processor. These spaces are given an order which corresponds to the order in which the instructions were read-in sequentially. The last position in the instruction buffer constitutes a read-out position (4). The results obtained when processing respective instructions can be saved in spaces allocated to these instructions in the instruction buffer (3), from which the results can be finally read-out from the read-out position (4).

Description

35 510 295 --- _ 2 _ The processor is adapted to, when reading a conditional jump instruction, predict the fulfillment of the condition, after which instructions are readable to, and machinable by, the processor according to the prediction immediately after reading the conditional jump instruction. An incorrect prediction results in subsequent read and partially processed instructions being removed from the processor to make room for a reading of correct instructions according to the fulfillment of the condition.

PRIOR ART In order to further simplify the understanding of the prior art and the present invention, some terms that will be used in the following description will be defined herein.

When reading an instruction, processing it and reading out the processed result takes place in different steps. When reading the instruction to a processor, a possible processing of the instruction is prepared. An instruction usually includes two operands and an operation to be applied to these operands.

The preparation of the instruction includes, among other things, a so-called "Fetch step". This step involves obtaining operand values because the instruction itself often, but not always, contains only an address to a position in a memory where the value of the operand is located.

A Fetch step can take different lengths of time for different instructions depending on where different operand values are to be retrieved from. This means that a first instruction read before a second instruction is processed after the later read second instruction because the operand values for the second instruction are available faster than the operand values for the first instruction. Thus, the result of the second instruction can be completed in the instruction buffer before the result of the first instruction.

An instruction is processed in a part of the processor called the Arithmetic Logical Unit (ALU).

Since the ALU does not need to process the instructions in sequence order, the waiting times for the ALU, in the case where the Fetch step for an instruction takes a long time, can be reduced.

In the event of an incorrect prediction of the fulfillment of a conditional jump instruction, incorrectly read instructions will be removed from the processor. This is called "flushing" of the processor.

The general method of predicting the fulfillment of a condition, as described above, is shown, for example, in patent publication EP-A2-0 706 121.

Many different ways of reducing the detrimental effect of an incorrect prediction of the fulfillment of a conditional jumping instruction are known.

Publication US-A-5 381 532 describes a processor which uses an alternative input buffer, a branch buffer (B). When reading a conditional jump instruction, the instructions according to the prediction for the fulfillment of the condition are read in sequentially after the conditional jump instruction and the instructions that must be obtained if the prediction is incorrect are read and stored in the branch buffer.

In the event of a possible flushing of the processor, the correct instructions are already loaded in the branch buffer and are thus immediately available to the processor. This reduces the time loss that an incorrect prediction and subsequent flushing entails.

The publications US-A-5 127 091, US-A-5 539 911, US-A-5 237 664 10 15 20 25 30 35 510 295 _ 4 _ and US-A-4 742 451 show and describe other solutions which are based on on the use of a parallel buffer for reading branch instructions.

It is also previously known to refine the algorithm that calculates the probability that a condition for a conditional jump instruction must be met and thereby thereby reduce the number of incorrect predictions. The publication "A Tour of the Pentium (R) Pro Processor Microarchitecture": Intel Corporation, describes a processor where only one input is used in the processor and assumes that the predicted fulfillment of a condition is correct.

This provides a very fast and efficient handling with correct predictions but entails a total flushing of the contents of the processor in the event of an incorrect prediction without the correct instructions being ready in an alternative buffer.

It should also be mentioned that a more accurate prediction requires a higher capacity in the statistical evaluation of the fulfillment of the conditions than a less accurate prediction requires.

It is also known to allow a conditional jump instruction to be preceded by a condition-testing instruction. This instruction is preferably so far before the jump instruction itself that it has time to execute and leave its result before the jump instruction itself enters the processor input.

When the conditional jump instruction is read into the processor, the result for the fulfillment of the condition is already known through the previous execution of the condition-testing instruction and the correct instructions can be read directly after the conditional jump instruction.

No instruction whose results may affect the condition of the conditional jump instruction may lie between the conditional jump instruction and the conditional jump instruction and whether the condition test instruction can be placed far enough ahead of the conditional jump instruction. thus depends on whether instructions that may affect the fulfillment of the condition are close to, or just before, the jumping instruction itself.

This restriction entails difficulties in software development and in some cases time delays in the introduction of empty instructions between a condition-testing instruction and the associated conditional jump instruction.

Publications GB-A-2 293 671 and EP-A2-0 509 245 both describe a computer or computer architecture which is mainly based on the computer comprising a separate processor intended to process conditional jump instructions separately from, and in parallel with, other instructions. .

It should also be mentioned that the instructions handled within a processor can be divided into two types of instructions in a simplified manner, processor-external instructions and processor-internal instructions.

For example, instructions in assembler code can be called processor-external instructions, while the instructions obtained after the assembler code has been converted to micro-code can be called processor-internal instructions.

It is also known in these contexts that a processor-external instruction normally forms a series of processor-internal instructions during the conversion.

It is also known that even if a processor external instruction does not include a conditional jump instruction, such instruction may result in a processor internal conditional jump instruction when converting from a processor external code to a processor internal code. PRESENT INVENTION TECHNICAL PROBLEMS Considering the prior art, as described above, it should be considered a technical problem that, based on a processor using predictions, of fulfilling the condition of a conditional jump instruction for reading subsequent instructions to the processor, where each loaded instruction is allocated space in an instruction buffer referred to herein, which spaces are allocated to a mutual order corresponding to the sequential order, and which instruction buffer comprises at least one last position within the instruction buffer which constitutes a readout position, from which the results from the processing of the respective instruction are readable in the sequential order, where an incorrect prediction results in subsequent loaded and partially processed instructions being deleted out of the processor to make room for a load of correct instructions according to the fulfillment of the condition, be able to realize how the time losses in the event of a flushing of the processor can be reduced in relation to known technology.

It is also a technical problem to be able to realize how a faster Fetch step and a higher utilization rate of the processor can be offered in relation to known technology, in the event of a possible flushing of the processor.

It is a technical problem to be able to realize how this can be offered without using condition-testing instructions that precede the conditional jump instruction or a separate processor for processing conditional jump instructions.

It is a technical problem to be able to realize how the accuracy of the prediction can be evaluated before the result from the processing of the conditional jump instruction has reached the reading position 10 15 20 25 30 35 510 295 in the position.

It is a technical problem to be able to realize how a flushing of the processor can take place correctly in the event of an incorrect prediction when the result from the processing of the conditional jump instruction has not yet reached the readout position.

It must be considered a technical problem to be able to realize how to obtain correct instructions in the event of an incorrect prediction, and how this should be adapted to different processor architectures.

It is a further technical problem to be able to realize how a processor should be adapted in terms of hardware in order to be able to offer an opportunity to evaluate the accuracy of a prediction of a condition fulfillment before the result of processing the conditional jump instruction reaches the reading position. prediction, be able to perform a correct flushing of the processor.

It is also a technical problem to be able to realize how a method or processor according to the present invention can be adapted to also make a processor more efficient in the handling of processor-internal conditional jump instructions.

Solution In order to be able to solve one or more of the above-mentioned technical problems, the present invention is based on a method for handling specific instructions, so-called conditional jump instructions, in a computer processor, where each loaded instruction is allocated space in an instruction buffer referred to herein. fourth, which spaces are assigned a mutual order corresponding to the sequential order according to which the respective instruction is loaded into the processor. At least one last position within the instruction buffer constitutes a read position from the instruction buffer. After the instructions have been processed by the processor, the result of the processing is storable in the respective space belonging to the instruction in the instruction buffer, in order to finally be readable from the reading position in the sequential order.

The processor is adapted to, when reading a conditional jump instruction, predict the fulfillment of the condition, after which instructions are readable to, and machinable by, the processor according to this prediction immediately after reading the conditional jump instruction.

An incorrect prediction results in subsequent read-in and partially processed instructions being removed from the processor to make room for a reading of correct instructions according to the fulfillment of the condition.

Based on such a method, the present invention specifically indicates that the outcome of the processing of the conditional jump instruction, and thus the knowledge of the fulfillment of associated conditions, is made available for evaluation before the space within the instruction buffer, belonging to the conditional jump instruction, reaches the read position.

Furthermore, the present invention teaches that deletion of instructions from the processor only affects instructions that are sequentially loaded according to the conditional jump instruction, regardless of where they are in the processing of instructions, in the event of an incorrect prediction of the fulfillment of the condition.

With the aim of offering an opportunity to further utilize the time gain obtained by advancing the knowledge of whether a prediction of whether a conditional jump instruction is correct or not, a method according to the present invention further teaches that an acquisition of the 15 20 25 30 35 510 235 _ 9 _ the correct instructions begin immediately with the knowledge of the fulfillment of the condition if the prediction was incorrect.

The present invention further provides a method based on processing a processor-internal instruction as described above with respect to conditional jump instructions, i.e. the result of a check of the fulfillment of a prediction concerning a processor-internal condition jump instruction is made available and considered as soon as it is clear, even if the space in the instruction buffer, belonging to the processor-internal conditional jump instruction, has not yet reached a readout position in the instruction buffer.

The present invention is also based on a processor, which comprises: a reading unit, intended to read instructions to the processor from a memory with sequentially consecutive instructions, some of which are so-called conditional jump instructions, where the fulfillment of the condition determines whether they instructions that follow sequentially directly after the conditional jump instruction must be loaded into the processor or if a jump in the sequence of instructions is to be made, which jump causes subsequent instructions to be loaded from somewhere else in the sequence according to the conditional jump instruction, - an instruction buffer , wherein space is allocable for respective loaded instructions, which spaces are assigned a mutual order corresponding to the sequential order and where at least one last position within the instruction buffer constitutes a reading position from the instruction buffer, - a processing unit, which is adapted to process in read instructions, after which the result of the processing is storable in the space belonging to the respective instruction in the instruction buffer, - a controlling unit, which is adapted to check whether the readout position comprises a result from a processing , - a reading unit, which is adapted to read the result from the reading position, - a predictive unit, which is adapted to, when reading a conditional jump instruction, predict the fulfillment of the condition, the reading unit being adapted to read instructions to the processor according to the prediction immediately after reading the conditional jump instruction, - an evaluation unit, which is adapted to evaluate whether the condition of the conditional jump instruction is met according to the prediction provided by the predictive unit, and - a removal unit which is adapted to remove from pro cessor loaded and partially processed in instructions read to the processor according to the conditional jump instruction if the prediction turned out to be incorrect.

Based on such a processor, the present invention specifically discloses that the processor comprises a result indicating unit, which is adapted to indicate when the result of the processing of a conditional jump instruction is stored in the position of the conditional jump instruction within the instruction buffer.

Furthermore, it is indicated that the evaluating unit is adapted to obtain the result from the processing of the conditional jumping instruction when this is available according to the performance indicating unit, whereby the evaluation is possible of whether the condition for the conditional jumping instruction is met or 10 15 20 25 30 35 5,111 _29 5 _ 11 _ not according to the prediction made by the predictive unit.

The present invention also teaches that the removal unit is adapted to only remove instructions from the processor that are sequentially loaded according to the conditional jump instruction, regardless of where they are in the processing of instructions, at a signal from the evaluating unit showing that the prediction of the fulfillment of the condition was incorrect.

A processor according to the present invention is also adapted to start a reading of correct instructions immediately after the evaluating unit has given results as to whether a prediction was correct, in the event that the prediction turned out to be incorrect.

Furthermore, the present invention, based on a processor comprising a converting unit, which is adapted to convert processor external instructions to processor-internal instructions, indicates that the above units are also adapted to process, and evaluate the result of such a process. processing, of both a processor-internal conditional jump instruction and a processor-external conditional jump instruction as above.

ADVANTAGES The advantages that can mainly be considered to be characteristic of a method and a processor adapted to operate according to the method according to the present invention are that the time loss caused by flushing according to known technology can be reduced. It is also the case that the Fetch step can be made faster and the capacity of the ALU (or ALUs can be several) can be released for processing any pending instructions that are not to be flushed. Furthermore, in the event of incorrect predictions, correct instructions can be read into the processor at an earlier stage than what is permitted with known technology. These factors together offer that the processor's capacity can be utilized to a greater extent than before.

The principle is simple and not tied to specific processor architectures, which means that it can easily be implemented in different processor architectures.

What may primarily be considered as characteristic of a method, in accordance with the present invention, is set forth in the characterizing part of the appended claim 1, and what may primarily be considered as characteristic of a processor, in accordance with the present invention, is set forth in the characterizing part of the appended patent claim 5.

BRIEF DESCRIPTION OF THE DRAWINGS A method and a processor adapted to operate according to the method, exhibiting the peculiarities associated with the present invention, will now be described in more detail by way of example with reference to the accompanying drawing, in which; Figure 1 shows schematically and very simply a processor.

DESCRIPTION OF THE NOW PROPOSED EMBODIMENT Instructions in a program code can be divided into mainly two types, flow-changing instructions and non-flow-changing instructions.

A non-flow-changing instruction, which is the most common, is of the read, write and arithmetic operations type. These usually comprise two operands, an instruction 10 15 20 25 30 35 510- ”295 _ 13 _. information on which operation is to be applied to the operands, as well as a destination address for the result of the operation.

Flow-changing instructions change the flow of instructions and cause a jump in the program code. The most common type of flow-changing instructions are so-called conditional jumps or conditional jump instructions. These also include two operands and an instruction on which operation is to be applied to the operands. This operation is usually a comparison between the operands where the condition for the jump consists in the similarity or difference of the operands.

No destination address is necessary for conditional jump instructions as the result of the operation is used locally in the processor to determine whether a jump in the flow should be made or not, however there is nothing to prevent a destination address from being used.

The instructions are read into a processor sequentially and several instructions may be in different stages of processing in the processor simultaneously. For exemplary purposes, Figure 1 shows a processor 1 where eight instructions can be processed 'simultaneously'. The instructions are read from a program memory 2 and assigned a space in an instruction buffer 3 referred to herein, which acts as a First In First Out (FIFO) buffer with eight positions 31, 32, ..., 38 shown here.

The results from each operation are read out from the instruction buffer 3 and printed to the intended destination address when the instruction in question is in a so-called readout position 4 within the instruction buffer, which in this example consists of the last position in the instruction buffer 3. However, It is very possible that the processing or execution of the operation was performed when the instruction was in a previous position in the instruction buffer. 10 15 20 25 30 35 510 295 ._ _- vid - 14 - The operation of a processor will be described in more detail to simplify the understanding of the present invention.

According to this example, a processor 1 has a dual input port with two different inputs, a first 111 and a second 112 input port, and associated first 113 and second 114 buffers, respectively, through which the instructions are obtained. A processor internal selector 12 determines from which input the instructions are to be retrieved.

When a conditional jump instruction 21 enters the processor, for example via the first input 111, and if this condition is highly probable, if it can be predicted, the instructions 22 according to the jump are immediately read in via the second input 112 where the associated buffer 114 is filled with subsequence. - giving instructions. The instructions 23 after the conditional jump 21 continue to be read in via the first input port 111 and stored in the first buffer 113.

The processor internal selector 12 retrieves instructions from the second buffer 114 as predicted. In the event of an incorrect prediction, the correct instructions wait in the first buffer 113 and these can be read into the processor after a flush of the incorrectly read instructions.

It is also conceivable that a processor only uses a single input port. When predicting the outcome of a conditional jump instruction, the instructions according to the prediction are then read into the only input, which means that in the event of an incorrect prediction, it takes longer to read the correct instructions than if two inputs are used, as these not loaded and waiting in an alternative input port.

The prediction of the fulfillment of the condition can be based on different algorithms, such as static or dynamic prediction.

Choosing to always assume that the condition is fulfilled, or 10 15 20 25 30 35 510 29.5 _15- is not fulfilled, is a so-called static prediction.

A prediction can also be based on a dynamic processing of how this condition has been met in the past. The statistical outcome of the fulfillment of different conditions is then saved in a list which is updated each time a conditional jump instruction is executed and which forms the basis for the predictions of whether these conditions are met or not. This is a dynamic prediction.

This previously known method means that if the condition, according to the prediction, is met, the correct instructions according to the jump follow immediately after the jump instruction in the instruction buffer and these can be executed and be ready to submit their results to their destination addresses immediately after the conditional jump instruction reaches the read position. 4 in the instruction buffer 3 and there left the result from the operation which determined whether the condition for the jump is met or not.

The present invention is independent of whether one or more entries are used, or what type of algorithm is used to predict the fulfillment of the condition used.

Regardless of the processor or algorithm type, the instructions that are being processed in the instruction buffer must not be executed in the event of an incorrect prediction, which is why a removal, or flushing, of these must be done so that the correct instructions can be read down. to the instruction buffer to be processed.

The processing of an instruction in a processor comprises several different steps.

A first step is to convert the code representing the instruction to a processor internal code. This conversion takes place in a converting unit, in this exemplary embodiment a so-called Assembler to micro code Translator Unit (ATU) 5, which converts instructions in assembler to instructions in machine language, after which the converted code is placed in instruction buffers 3.

The ATU 5 also includes the processor internal selector 12 and its control.

The space in the instruction buffer comprises various fields, some of which are shown in position 31 in the instruction buffer 3, comprising a field for operand A (OPA) 31A, a field for operand B (OPB) 31b, a field for operation (ALSO) 3lC and a field with the destination address of the result (DEST) 3lD.

A second step is a so-called Fetch (retrieval) where necessary operands are retrieved from different memories M1, M2 if these are not available in the instruction itself. Depending on which memory an operand is to be read from, this can take different lengths of time. Some memories may be processor internal memories M1 and others may be memories positioned outside of processor M2.

When the operands are retrieved, the next step can be taken which is an execution of the instruction where the operands 31A, 31B and the instruction 31C are sent to an ALU 6 where the instruction is executed and a result is left to a result field 31I.

When the position of the instruction in the instruction buffer has reached the readout position 4, the next step is performed provided that the result from the ALU 6 is ready and left to the result field 31I. This step is a so-called Commit or Write Back where the result is written to the address according to the contents of the field for the destination address 3lD.

Execution does not necessarily have to be performed sequentially but can be performed as soon as the Fetch step for an instruction is performed. This means that some instructions may be ready for 10 15 20 25 30 35 5111295 _17 ..

Commit even though instructions that are sequentially ahead of the instruction buffer are not yet complete with Fetch.

Flushing in case of an incorrect prediction takes time and capacity from the processor. In the event that a processor is used that uses two inputs, this provides a certain degree of protection that enables a preparation of the instructions to be read in after a flush in connection with an incorrect prediction.

This guarding means that the correct instructions are ready in the first buffer 113, but it is still a large, and in these contexts expensive, operation to have to flush all the contents of the processor, i.e. in the instruction matrix 3, where many of the instructions may already be executed and ready for Commit.

In the case of a processor with a simple input port, the time losses due to a flushing in the event of an incorrect prediction are even greater.

The invention is based on an early jump report which means that the result 3IE from the execution of a conditional jump instruction can be used before the conditional jump instruction reaches the reading position 4 in the instruction buffer 3. The earlier this result is known, the less detrimental effect a flush gives. correct instructions are obtained, in the event of an incorrect prediction of the fulfillment of the condition.

When the execution step for a conditional jump instruction is performed, the result of the execution is available in the processor. According to prior art, this result is not used until the conditional jump instruction has reached the position of the Commit, i.e. the readout position 4.

The invention is thus based on the fact that the result of an execution of a conditional jump instruction is used as soon as it is available 15 15 25 25 30 35 510 295 _ 13 _.

This is done by adapting the ATU 5 to monitor the processing of a conditional jump instruction in the processor and as soon as this instruction is executed, the result is used to determine the accuracy of the prediction of the fulfillment of the condition.

With a correct prediction, the process is allowed to continue. In the event of an incorrect prediction, all instructions that follow the conditional jump instruction in the read sequence are flushed.

This means that not all instructions in the processor should be flushed because there may still be, and probably are, instructions in the processor that are sequentially before the conditional jump instruction and thus not affected by the jump but which are still not finished with, for example, Fetch.

This means that flushing does not refer to everything in the processor but only to certain instructions. These instructions may have come differently in their processing in the processor. Regardless of where they are in this processing, subsequent instructions are flushed and capacity is released for executing instructions that have not yet reached the step of execution but are not to be flushed.

A processor that is adapted to operate according to the method described above will now be described in more detail.

A processor of a known type simply comprises: - a loading unit, here referred to as input lll with associated buffer 113, intended to read instructions to the processor from a memory 2 with sequentially consecutive instructions, - an instruction buffer 3, in which a space 31, 32, ..., 38 is assignable to the respective read instruction, where at least one last position within the instruction buffer 3 constitutes a readout position 4 from the instruction buffer, a processing unit, here referred to as ALU 6, which is adapted to process loaded instructions, after which the result of the processing is storable in the space 313 belonging to the respective instruction in the instruction buffer 3, a controlling unit 13, which is adapted to check whether the reading position comprises a result from a processing, - a reading unit 14, which is adapted to read the result from the reading position 4, - a predictive unit 15, which is adapted to, when reading a conditional jump instruction, predict the fulfillment of the condition, - an evaluating unit 16, which is adapted to evaluate whether the condition of the conditional jump instruction is fulfilled according to the prediction made by the predictive jump instruction. unit, and - a removal unit 17 which is adapted to remove from the processor read and partially processed instructions which are read into the processor according to the conditional jump instruction if the prediction is found to be incorrect.

Starting from such a processor 1, the present invention specifically discloses that the processor also comprises a result indicating unit 18, which is adapted to indicate when the result of the processing of a conditional jump instruction is stored in the position of the conditional jump instruction within the instruction buffer.

It is further indicated that the evaluating unit 16 is adapted to obtain the result 3IE from the processing of the conditional jump instruction when this is available according to the result indicating unit 18, the evaluation being possible of whether the condition for the conditional jump instruction is fulfilled or not according to the prediction made by the predictive unit 15. This retrieval of the result is thus possible regardless of whether the position of the conditional jump instruction is in the readout position 4 within the instruction buffer 3 or not.

The present invention also provides that the removal unit 17 is adapted to only remove instructions from the processor which are sequentially loaded after the conditional jump instruction, regardless of where they are in the processing of instructions, at a signal from the evaluating unit 16. which shows that the prediction of the fulfillment of the condition was incorrect.

In the above description, reference is made to conditional jump instructions read from a program memory 2. When such an instruction is converted in the converting unit 5 to micro-code, such a processor external instruction probably constitutes a plurality of processor-internal instructions in micro-code.

There are also examples of processor-external instructions that do not include a conditional jump but where its equivalent in processor-internal code includes a conditional jump instruction.

For example, a processor-external instruction without conditional jump instructions translated into micro-code can result in a processor-internal loop with a conditional jump instruction, where the condition is that the loop must be broken when a certain condition is met.

Thus, the present invention also encompasses a method of handling processor-internal conditional jump instructions in a data processor where the conditional jump instructions do not necessarily result from a processor-external conditional jump instruction 10 15 20 25 30 35 510 295 _ 21 _ instruction.

The fulfillment of the condition determines whether the instructions that follow sequentially directly after said conditional jump instruction are to be processed by the processor or whether a jump in the sequence of processor-internal instructions is to be made.

Such a jump means that subsequent processor-internal instructions must be read from somewhere else in the sequence, or from subsequent converted processor-external instructions, according to the conditional jump instruction.

An incorrect prediction of the fulfillment of the condition results in subsequent read and partially processed processor-internal instructions being flushed to make room for a reading of, according to the fulfillment of the condition, correct processor-internal instructions.

In this case, not all instructions in the processor are deleted because there are still loaded processor-external instructions that have not yet been converted to processor-internal instructions and that are not affected by the processor-internal conditional jump instruction.

When a processor-internal conditional jump instruction is found, the subsequent processor-external instruction is not loaded into the ATU 5 for conversion, which means that in the event of a deletion of instructions due to an incorrect prediction of a condition being fulfilled, only processor-internal instructions removed and the next processor-external instruction can be loaded into the ATU 5 for conversion.

In particular, the present invention teaches that the outcome of the processing of a conditional jump instruction, and thus the knowledge of the fulfillment of the condition, is made available for evaluation as soon as the processing is completed, even if this occurs before the space within the instruction buffer, belonging to 35 s1o_ 295 _ _ 22 _ the conditional jump instruction, reached the readout position 4.

Furthermore, the present invention provides that, in the event of an incorrect prediction of the fulfillment of the condition, the deletion of instructions from the processor only affects processor-internal instructions which are sequentially loaded after the conditional jump instruction, regardless of where they are in the processing of instructions.

A processor adapted to also take into account processor-internal conditional jump instructions shall, like the previously described processor, comprise a result indicating unit 18, which is adapted to indicate when the result of the processing of a conditional jump instruction is stored in the position of the conditional jump instruction within the instruction buffer.

It also comprises an evaluation unit 16 which is adapted to obtain the result of the processing of the processor-internal conditional jump instruction when this is available according to the result-indicating unit 18.

In this case, it is possible for the evaluating unit 16 to carry out an evaluation of whether the condition for the processor-internal conditioned jumping instruction is fulfilled or not according to the prediction made by a predictive unit 15.

Furthermore, the present invention provides that a removal unit 17 is adapted to remove processor-internal instructions from the processor which are sequentially loaded after the processor-internal conditional jump instruction, regardless of where they are in the processing of instructions, at a signal from the processor. evaluation unit 16 which shows that the prediction of the fulfillment of the condition was incorrect.

The invention is of course not limited to the embodiment stated above as an example, but may undergo modifications within the scope of the inventive concept illustrated in the following claims.

Claims (12)

10 15 20 25 30 35 '510 295 _ _ 24 _ PATENTKRAV A method for handling specific instructions, so-called conditional jump instructions, in a computer processor, wherein said conditional jump instruction is one of several sequentially read instructions to said processor, wherein the fulfillment of the condition determines whether the instructions sequentially follow directly after said conditional jump instruction shall be loaded into said processor or if a jump in said sequence of instructions is to be made, which means that subsequent instructions shall be loaded from another location in said sequence according to said conditional jump instruction, where space is allocated respectively loaded. instruction in an instruction buffer referred to herein, wherein said spaces in said instruction buffer are assigned a mutual order corresponding to said sequential order and where at least one last position within said instruction buffer constitutes a readout position from said instruction buffer, after which said instructions are bea processable by said processor and after which the result of said processing is storable in respective space belonging to said instruction in said instruction buffer, to finally be readable from said readout position in said sequential order, and where said processor, at the reading of a conditional jump instruction, predicts fulfillment of the condition, after which instructions are readable to, and editable by, said processor according to said prediction immediately after reading said conditional jump instruction, where an incorrect prediction results in subsequent loaded and partially processed instructions. is removed from said processor to provide space for a reading of, according to the fulfillment of said conditions, correct instructions, characterized in that the outcome of the processing of said conditional jump instruction, and thus the knowledge of the fulfillment of said conditions, is made available for evaluation as soon as namely This processing is carried out, even in the case where this takes place before the space within said instruction buffer, belonging to said conditional jump instruction, reaches said readout position. Method according to claim 1, characterized in that, in the event of an incorrect prediction of the fulfillment of said conditions, said removal of instructions from said processor only affects instructions which are sequentially loaded according to said conditional jump instruction, regardless of where they are located. in said processing of instructions. Method according to claims 1 and 2, wherein the reading of instructions to said processor takes place via a simple input, characterized in that the reading of said correct instructions begins directly with an available knowledge that an incorrect prediction of the fulfillment of a condition belonging to a conditional jump instruction, and that this loading takes place via the said simple input. A method according to claims 1 and 2, wherein the reading of instructions to said processor takes place via one of two inputs, with associated buffers, belonging to a double input, and where, in the case of a reading of a conditional jump instruction, the reading of instructions according to a prediction of the fulfillment of said conditional jump instruction are read into said processor via a first input belonging to said double input and the reading of instructions according to a second possible outcome of the fulfillment of said conditional jump instruction is read into said processor via a second input belonging to said double input, where read instructions are stored in the respective buffer, characterized in that the reading of said correct instructions begins directly with an available knowledge that an incorrect prediction of the fulfillment of a condition belonging to a conditional jumping instruction, and that this loading takes place from the buffer belonging to said other i nport. Processor, comprising a loading unit, intended to read instructions to the processor from a memory with sequential instructions in succession, some of which are so-called conditional jump instructions, where the fulfillment of the condition - determines whether the instructions sequentially following directly after said conditional jump instruction are to be read into said processor or whether a jump in said sequence of instructions is to be made, which means that subsequent instructions are to be read from somewhere else in said a sequence according to said conditional jump instruction, an instruction buffer, wherein space is allocable and loaded instruction, respectively, which spaces are assigned a mutual order corresponding to said sequential order and where at least one last position within said instruction buffer constitutes a readout position from said instruction buffer, a processing unit, which is adapted to process said instructions, after which the result of said processing is storable in the respective space belonging to said instruction in said instruction buffer, a controlling unit, which is adapted to check whether said reading position comprises a result of a processing, a reading unit, which is adapted to read said result from said readout position, a predictive unit, which is adapted to, when reading a conditional jump instruction, predict the fulfillment of the condition, said reading unit being adapted to read instructions to said processor according to said prediction immediately after reading said conditional jump instruction, an evaluation unit, which is adapted to evaluate whether the condition of said conditional jump instruction is met according to the prediction made by said predictive unit, and a removal unit which is adapted to remove loaded and partial processed instructions read into said processor after said conditional jump instruction from said processor if said prediction proved to be incorrect, characterized in that said processor comprises a result indicating unit, which is adapted to indicate when the result of the processing of a conditional jump instruction is stored in the position of said conditional jump instruction within said instruction buffer, and that said evaluating unit is adapted to obtain the result of said processing of said conditional jump instruction when this is available according to said result-indicating unit, said evaluation of whether the condition for said conditional jumping instruction is fulfilled or not according to the prediction made by said predictive unit being possible. Processor according to claim 5, characterized in that said removing unit is adapted to remove instructions from said processor which are sequentially loaded according to said conditional jump instruction, regardless of where they are in said processing of instructions, at a signal from said evaluating unit showing that said prediction of fulfillment of said conditions was incorrect. Processor according to claims 5 and 6, which is assigned a simple input whereby the reading of instructions to said processor takes place, characterized in that said processor is adapted to start a reading of said correct instructions directly at a signal from said evaluator. unit which shows that said prediction of the fulfillment of said conditions was incorrect, and that this loading takes place via said simple input. A processor according to claims 5 and 6, which is assigned a dual input port, with a first and a second input port and associated buffers, which processor is adapted to read instructions to via one of said two input ports, and there, said processor is adapted to, when reading a conditional jump instruction, read instructions according to a prediction of the fulfillment of said conditional jump instruction via said first input belonging to said double input and instructions according to a second possible outcome of the fulfillment of said conditional jump instruction via said second input port belonging to said dual input port, where the respective buffer is adapted to store read instructions, characterized in that said processor is adapted to start a reading of said correct instructions directly at a signal from said evaluation unit showing that said prediction of the fulfillment of said conditions was incorrect, and that this loading takes place from the buffer belonging to said second input port. A method of handling specific instructions, so-called conditional jump instructions, in a data processor, said processor comprising a converting unit, which converts instructions loaded into said processor on a processor-external code into a processor-internal code, where a processor-external instruction loaded into said processor can result in a sequence of different processor-internal instructions, some of which may consist of said conditional jump instructions, where the fulfillment of the condition determines whether the instructions that follow sequentially directly after said conditional jump instruction is to be processed by said processor or if a jump in said sequence of processor-internal instructions is to be made, which means that subsequent processor-internal instructions are to be read from somewhere else in said sequence, or from subsequent converted processor-external instruction, according to the said conditional jumping instruction, where space is allocated respective internal processor instructions in an instruction buffer referred to herein, wherein said spaces in said instruction buffer are assigned a mutual order corresponding to said sequential order and wherein at least one last position within said instruction buffer constitutes a readout position from said instruction buffer, after which said instructions are machinable by said processor and then the result of said machining is storable in the respective space belonging to said instruction in said instruction buffer, to finally be readable from said readout position in said sequential order, and where said processor, upon reading a conditional jump instruction, predicts fulfillment of the condition, after which instructions are machinable by said processor in an order 10 15 20 25 30 35 s1o * 29s _ 29 - according to said prediction immediately after reading said conditional jump instruction, where an incorrect prediction results. i that subsequently read and partially processed processor-internal instructions are removed from said processor to make room for a reading of, according to said conditions, correct processor-internal instructions, characterized in that the outcome of the processing of said conditional jump instruction , and thus the knowledge of the fulfillment of said conditions, is made available for evaluation as soon as said processing has been completed, even in the case where this takes place before the space within said instruction buffer, belonging to said conditional jump instruction, reaches said reading position. Method according to claim 9, characterized in that, in the event of an incorrect prediction of the fulfillment of said conditions, said removal of instructions from said processor only concerns processor-internal instructions which are sequentially loaded according to said conditional jump instruction, regardless of where they are located. in the said processing of instructions. 11. ll. Processor, comprising a converting unit, which is adapted to convert instructions read into said processor on a processor external code into a processor internal code, where a processor external instruction loaded into said processor can result in a sequence of different processor-internal instructions, some of which may consist of conditional jump instructions, where the fulfillment of the condition determines whether the instructions sequentially following directly after said conditional jump instruction are to be processed by said processor or whether a jump in said sequence of processor-internal instructions must be made, which means that subsequent processor-internal instructions must be read from some other place in said sequence, or from subsequent converted processor-external instruction, according to said conditional jump instruction, an instruction buffer, in which space is allocated - 10 15 20 25 30 35 510 295 _ _ 30 _ bare and loaded instruction, which spaces are assigned a mutual order corresponding to said sequential order and where at least one last position within said instruction buffer constitutes a readout position from said instruction buffer, a processing unit which is adapted to process said instructions, after which the result of said processing is storable. in the respective space belonging to said instruction in said instruction buffer, a controlling unit, which is adapted to check whether said reading position comprises a result from a processing, a reading unit, which is adapted to read said result from said reading position, a predictive unit, which is adapted to, in the case of a processor-internal conditional jump instruction, predict the fulfillment of the condition, said processing unit being adapted to process instructions according to said prediction immediately after reading said conditional jump instruction, an evaluating unit, which is adapted to evaluate whether the condition of said conditional jump instruction is met according to the prediction made by said predictive unit, and a deleting unit which is adapted to delete read and partially processed processor internal instructions loaded into said instruction buffer after said conditional jump instruction from said processor if said prediction is found to be incorrect, characterized in that said processor comprises a result indicating unit, which is adapted to indicate when the result from the processing of a conditional jump instruction is stored in the position of said conditional jump instruction. within said instruction buffer, and that said evaluating unit is adapted to obtain the result of said processing of said conditional jump instruction as this is available according to said result indicating unit, said evaluation of whether the condition of said processor internally The correct jump instruction is fulfilled or not according to the prediction made by the said predictive unit is possible. 510 295 '_ 31 _ Processor according to claim 11, characterized in that said removing unit is adapted to remove processor internal instructions from said processor which are sequentially loaded according to said conditional jump instruction, regardless of where they are in said processing of instructions, at a signal from said evaluating unit showing that said prediction of fulfillment of said conditions was incorrect.