SE9702762L - Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method - Google Patents

Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method

Info

Publication number
SE9702762L
SE9702762L SE9702762A SE9702762A SE9702762L SE 9702762 L SE9702762 L SE 9702762L SE 9702762 A SE9702762 A SE 9702762A SE 9702762 A SE9702762 A SE 9702762A SE 9702762 L SE9702762 L SE 9702762L
Authority
SE
Sweden
Prior art keywords
processor
instructions
read
conditional jump
operate according
Prior art date
Application number
SE9702762A
Other languages
Swedish (sv)
Other versions
SE510295C2 (en
SE9702762D0 (en
Inventor
Carl Tobias Roos
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9702762A priority Critical patent/SE510295C2/en
Publication of SE9702762D0 publication Critical patent/SE9702762D0/en
Priority to BR9810768-2A priority patent/BR9810768A/en
Priority to JP2000503482A priority patent/JP2001510916A/en
Priority to CN98809339A priority patent/CN1271434A/en
Priority to EP98934048A priority patent/EP0998701A2/en
Priority to PCT/SE1998/001334 priority patent/WO1999004335A2/en
Priority to KR1020007000634A priority patent/KR20010022065A/en
Priority to AU83652/98A priority patent/AU8365298A/en
Publication of SE9702762L publication Critical patent/SE9702762L/en
Publication of SE510295C2 publication Critical patent/SE510295C2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

The present invention relates to a method of handling conditional jump instructions in a computer processor (1). Space is allocated in a so-called instruction buffer (3) for respective instructions read into the processor. These spaces are given an order which corresponds to the order in which the instructions were read-in sequentially. The last position in the instruction buffer constitutes a read-out position (4). The results obtained when processing respective instructions can be saved in spaces allocated to these instructions in the instruction buffer (3), from which the results can be finally read-out from the read-out position (4).
SE9702762A 1997-07-21 1997-07-21 Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method SE510295C2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
SE9702762A SE510295C2 (en) 1997-07-21 1997-07-21 Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method
BR9810768-2A BR9810768A (en) 1997-07-21 1998-07-07 Process of handling specific instructions, and, processor
JP2000503482A JP2001510916A (en) 1997-07-21 1998-07-07 Processing method of conditional jump instruction in data processor
CN98809339A CN1271434A (en) 1997-07-21 1998-07-07 Method and processor adapted for handling of conditional jumps
EP98934048A EP0998701A2 (en) 1997-07-21 1998-07-07 A method for handling conditional jump instructions in a data processor
PCT/SE1998/001334 WO1999004335A2 (en) 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps
KR1020007000634A KR20010022065A (en) 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps
AU83652/98A AU8365298A (en) 1997-07-21 1998-07-07 A method for handling conditional jump instructions in a data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9702762A SE510295C2 (en) 1997-07-21 1997-07-21 Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method

Publications (3)

Publication Number Publication Date
SE9702762D0 SE9702762D0 (en) 1997-07-21
SE9702762L true SE9702762L (en) 1999-01-22
SE510295C2 SE510295C2 (en) 1999-05-10

Family

ID=20407793

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9702762A SE510295C2 (en) 1997-07-21 1997-07-21 Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method

Country Status (8)

Country Link
EP (1) EP0998701A2 (en)
JP (1) JP2001510916A (en)
KR (1) KR20010022065A (en)
CN (1) CN1271434A (en)
AU (1) AU8365298A (en)
BR (1) BR9810768A (en)
SE (1) SE510295C2 (en)
WO (1) WO1999004335A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US9952869B2 (en) 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
EP2367102B1 (en) * 2010-02-11 2013-04-10 Nxp B.V. Computer processor and method with increased security properties

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
CA1285657C (en) * 1986-01-29 1991-07-02 Douglas W. Clark Apparatus and method for execution of branch instructions
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
SE509499C2 (en) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Method and apparatus for handling conditional jumps in instructional processing in a pipeline architecture

Also Published As

Publication number Publication date
WO1999004335A2 (en) 1999-01-28
EP0998701A2 (en) 2000-05-10
BR9810768A (en) 2000-08-15
AU8365298A (en) 1999-02-10
WO1999004335A3 (en) 1999-04-08
SE510295C2 (en) 1999-05-10
KR20010022065A (en) 2001-03-15
SE9702762D0 (en) 1997-07-21
CN1271434A (en) 2000-10-25
JP2001510916A (en) 2001-08-07

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