KR100516214B1 - A digital signal processor for parallel processing of instructions and its process method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor for instruction parallel processing and a processing method thereof, and in particular, a digital signal processor applicable to a high performance signal processing system that accommodates the advantages of a superscalar structure and a VLIW (Very Long Instruction Word) structure. (Digital Signal Processor, hereinafter referred to as DSP).

The digital signal processor and the processing method thereof for parallel processing of instructions of the present invention include a first step of calculating the number of next instructions M that can be executed simultaneously, and a second step of selecting one maximum value from M calculated in the first step. A third step of grouping the instructions corresponding to the value selected in the second step; a fifth step if all instructions are grouped; otherwise a fourth step of performing the first step; There is a technical feature in that the algorithm is performed by the fifth step of rearranging the instructions according to the operation block to execute the corresponding instruction and assigning a tag value.

Accordingly, the digital signal processor and the processing method thereof for parallel processing of instructions of the present invention provide a DSP structure that can be applied to a high-performance signal processing system that adopts the advantages of a superscalar structure and a VLIW structure, using a simple flag. This allows the DSP to generate no operation instructions, reducing the program size, and simplifying the DSP structure by allowing the software (compiler and assembler) to construct instructions that can be processed in parallel.

Description

Digital signal processor for parallel processing of instructions and its process method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor for parallel processing of instructions and a method of processing the same, and in particular, a digital signal applicable to a high performance signal processing system that accommodates the advantages of a superscalar structure and a VLIW (Very Long Instruction Word) structure. The present invention relates to a digital signal processor (DSP).

With the rise of SDR (Software Defined Radio) technology, high performance DSPs are required for software to process signal processing systems such as communication, images, and video. In order to process the signal processing software at high speed, the currently used method is to use ILP (Instruction Level Parallelism). Commercially commercialized technologies for implementing the ILP can be classified into two categories.

Conventionally, there are two structures, a superscalar structure and a VLIW structure, as DSP structures, which are described in detail in Korean Patent Laid-Open Publication Nos. 193-0016896, 1999-0062575, 1992-0020340, and the like.

Superscalar structure depends on DSP for ILP implementation. That is, after reading a predetermined number of instructions from the memory where the instructions are stored, the DSP determines the instructions that can be processed simultaneously and processes them in parallel. If a command that cannot be processed at the same time among the read commands is determined again, the commands that can be processed in parallel with the next read commands are processed again. That is, in the case of the superscalar structure, since DSP executes the parallelism of instructions in hardware, the DSP structure is complicated, and an instruction buffer is required to store instructions that cannot be processed in parallel among the read instructions.

The VLIW architecture relies on software (compiler or assembler) for implementing ILP. That is, the instruction itself contains instructions to be executed by each operation module in the DSP to make one long instruction. At this time, the DSP reads a predetermined number of instructions from the memory in which the instructions are stored and delivers the instructions for the operation module to be performed in each operation module to the corresponding operation module for processing. Therefore, once read instructions are processed immediately, hardware is simpler than superscalar structure because there is no need for instruction buffer and no need to decide which instructions can be processed simultaneously.

However, such a prior art processor structure has a large number of no operation instructions when all the operation blocks cannot be executed at the same time. This is a command that the DSP does nothing, resulting in a larger program size. In particular, the Republic of Korea Patent Publication No. 199-0016896 introduces a calculator that can perform a parallel operation function using the advantages of the two structures by mixing the superscalar structure and the VLIW structure, as in the present invention, It does not present the algorithm.

Accordingly, the present invention is to solve the problems of the prior art as described above, because the superscalar structure and VLIW structure has advantages and disadvantages, respectively, in the case of companies currently selling commercial products, It proposes a more efficient DSP structure than conventional products. The present invention proposes a high-performance DSP structure capable of implementing such a signal processing system, and the proposed scheme proposes a DSP structure applicable to a high-performance signal processing system by accommodating the advantages of the superscalar structure and the VLIW structure. There is this.

The above object of the present invention is achieved by providing a DSP structure applicable to a high performance signal processing system that accommodates the advantages of a superscalar structure and a VLIW structure.

Details of the above object, technical configuration and effects according to the present invention will be described in detail with reference to the drawings showing preferred embodiments of the present invention.

First, let us look at four basic matters for the programming algorithm of the present invention.

First is a command and a tag. In the present invention, all instructions are defined by a fixed number of bits (eg, 32 bits). That is, all instructions are composed of the same number of bits, such as a reduced instruction set computer (RISC) processor. If the number of operation blocks that can be processed simultaneously in the DSP is e, the e-bit tag is included in each instruction. The included e-bit tag has information about the instruction set to be executed next. That is, as shown in FIG. 1, each instruction is composed of an actual instruction and an e-bit tag. FIG. 2 is a simplified block diagram of a DSP and includes a decode block and e operation blocks for reading and processing instructions. The tag consists of e-bit flags (hereinafter referred to as Flags), where each Flag indicates an operation block. 3 shows a tag in detail. The meaning of each flag is defined by Equation 1. Flag (i) (i = 1, 2, ...., e-1, e) = 0 or 1

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Here, when Flag (i) = 0, the operation block i may not be performed when performing the next operation. However, when Flag (i) = 1, the operation block i may be performed when the next operation is performed.

Therefore, the number of instructions Num to be processed next is calculated by Equation 2. Num = Flag (1) + Flag (2) + .... Flag (e-1) + Flag (e)

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For example, when an instruction and a tag are configured as shown in FIG. 4, after performing instruction 1, the DSP reads and processes the next three instructions. This is because Flag (2), Flag (3), and Flag (6) are 1 and the remaining Flags are 0. In this case, since Flag (1) is 0, the operation block 1 does not perform any operation when performing the next operation, and since the Flag (2) is 1, the instruction 2 is processed in the operation block 2. In the same way as above, Flag (3) is 1, so instruction 3 is processed in operation block 3. Since Flag (6) is 1, instruction 4 is processed in operation block 6. Will not process. That is, arithmetic instructions are transmitted to arithmetic block 1, arithmetic block 4, arithmetic block 5, arithmetic block 7, and arithmetic block 8. This is a DSP-generated instruction that does not exist in the instruction. That is, in the present invention, the DSP structure can be reduced by using a simple flag to reduce the program size and allow the software (compiler and assembler) to configure instructions that can be processed in parallel to simplify the DSP structure. have.

Second is the first command of the program. The first instruction in the program is necessarily an instruction, and the tag contains information about the instruction to be processed next. When the first command is executed after the DSP is reset, only one command is read and the flags included in the tag are analyzed to read the next command. This is because there is no tag information when the DSP starts executing instructions after it is reset, and it is impossible to determine how many instructions to read and in which operation block to process them.

Third, it is an unconditional branch instruction. In the case of an unconditional branch instruction, the tag may be predetermined because the destination address is predetermined. In this case, the tag becomes the tag of the instruction immediately before the destination instruction. That is, in the case of FIG. 5, Tag (B), which is a tag of an unconditional branch instruction, is obtained by the following equation. Tag (B) = Tag (N-1) Fourth, it is a conditional branch instruction. In the case of a conditional branch instruction, the tag cannot be predetermined because the destination address is not predetermined. After the conditional branch instruction, a no operation instruction is inserted. Tag of conditional branch instruction becomes tag to execute one instruction stored at address to branch when condition is satisfied. And the tag of the non-operational instruction after the conditional branch instruction becomes the tag for the next instruction to be executed.

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With the above four basic matters, the program creation (command placement) for the DSP structure proposed by the present invention is prepared according to Algorithm 1.

Algorithm 1

Step 1: Calculate the number of next instructions (M) that can be executed simultaneously for each instruction.

Step 2: Choose the maximum value from M calculated in step 1.

Step 3: Group the commands that correspond to the values you selected in Step 2.

Step 4: If all the commands are grouped, go to step 5; otherwise, go to step 1.

Step 5: Relocate the instructions in each group according to the operation block to execute the instruction, and assign the tag value to the instruction.

When an instruction is placed by Algorithm 1, the instructions are placed in a group in the order of the operation block in which the instruction is to be executed. In other words, Operation block The command that can be executed in satisfies Equation 4 in one group. Here, AddressOf (X) represents the address of the memory where the X command is stored. ) <AddressOf ( )-> m <n

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Next, a program creation (command placement) method will be described by way of example.

No operation as the command to perform, , , , , , Assuming that the same instruction is executed, Table 1 shows the number (M) of the next instructions that can be executed simultaneously in the first step of Algorithm 1.

 command  No operation     M    4     3     3     3     2     One    0

From step 2 of Algorithm 1, the following four instructions are formed into one group. Then, the last Wow This is a group.

If you rearrange the instructions in each group from step 5 of Algorithm 1, , , , , , Instructions are arranged as shown in Table 2, and the Tag value for each instruction is calculated.

command Tag No operation 11101 (Tag 1) 01101 00101 00001 11000 (Tag 5) 01000 00000

The DSP analyzes Tag 1 by reading the first no-operation instruction and Tag 1. Analyzing Tag 1 reveals that there are four instructions to perform next, so the DSP reads four instructions from the program memory. And since Flag (1) is 1, the first instruction is transferred to operation block 1. In the same manner as above, the second instruction is transferred to the operation block 2, and the third instruction is transferred to the operation block 3. Since Flag (4) is 0, no operation is transmitted to operation block 4, and the fourth instruction is transferred to operation block 5. Then, it analyzes Tag 5 and decides the next command to be read. The next number of instructions to read is two, passing the first instruction to operation block 1, and passing the second instruction to operation block 2.

The tag value of the last command in the group contains information about the next command group to be executed. The tag value for other instructions is determined as a tag value corresponding to the instructions remaining after the instruction in the group.

Accordingly, the digital signal processor and the processing method thereof for parallel processing of instructions of the present invention provide a DSP structure that can be applied to a high performance signal processing system that accommodates the advantages of a superscalar structure and a VLIW structure. The advantage of simplifying the DSP structure is that the DSP generates the instructions, reducing the program size and allowing the software (compiler, assembler) to construct instructions that can be processed in parallel.

1 is a simplified command diagram of the present invention.

2 is a simplified block diagram of a digital signal processor of the present invention.

3 is a block diagram of a tag of the present invention.

4 is a block diagram of the instruction before relocation of the present invention.

5 is an example of an unconditional branch instruction of the present invention.

Claims (13)

In the digital signal processing method, Calculating a number M of next instructions that can be executed simultaneously; A second step of selecting one maximum value from M calculated in the first step; A third step of grouping instructions corresponding to the value selected in the second step; Performing a fifth step if all the instructions are grouped, or performing a first step on the remaining instructions not created in the instruction group; And The fifth step of rearranging the instructions in each group according to the operation block to execute the instruction, and assigning a tag value Method of processing a digital signal processor for parallel processing instruction comprising a The method of claim 1, The method of the digital signal processor for parallel processing of instructions, characterized in that the instruction is a fixed number of bits. The method of claim 1, If the number of operation blocks that can be processed simultaneously in the digital signal processor e number of instructions, the method of processing a digital signal processor for parallel processing instructions, characterized in that each instruction includes an e-bit tag The method of claim 1, The number of instructions M is Num = Flag (1) + Flag (2) + .... Flag (e-1) + Flag (e), where e is the number of operation blocks and Flag (e) is Method of processing a digital signal processor for parallel processing of instructions, characterized in that the calculation is performed by an indicator indicating an operation block). The method of claim 4, wherein When Flag (i) (i = 1, 2, ...., e-1, e) = 1, the operation block i can be executed when performing the next operation. How to deal with The method of claim 1, Method of processing a digital signal processor for parallel processing of instructions characterized in that the first instruction of the instruction is a non-operational instruction The method of claim 6, When the first command is executed after the digital signal processor is reset, only one command is read, the flags included in the tag are analyzed, and the next command is read. The digital signal processor for command parallel processing is as follows. How to deal with The method of claim 1, The tag includes information about a command to be processed next, the digital signal processor processing method for parallel processing instructions The method of claim 1, The tag of the unconditional branch instruction becomes the tag of the instruction immediately before the destination instruction. The method of claim 1, A method of processing a digital signal processor for parallel processing of instructions, characterized in that a non-operational instruction is inserted after the instructions of the conditional branch. The method of claim 10, The tag of the instruction of the conditional branch is a tag for executing one instruction stored in the address to branch when the condition is satisfied, the method of processing a digital signal processor for parallel processing of instructions The method of claim 11, The tag of the non-operational instruction next to the conditional branch instruction becomes a tag for the next instruction to be executed. Digital signal processor for instruction parallel processing, characterized in that the algorithm is performed by the method of claim 1