KR100829167B1 - Method of reducing data dependence for software pipelining - Google Patents

Abstract

A method for reducing data dependence in software pipelining is provided to improve the performance of a pipelining loop of a DSP(Digital Signal Processor) and utilize resources of the DSP fully by reducing the data dependence in iterated pipelining. All routes is searched from a data dependence graph made for machine language of a target loop code and a priority route forming the longest route, which determines an execution time of the loop, is found from the searched routes(S200). An instruction having the shortest priority route is found as an instruction to reduce dependence by forming a replaceable instruction table for the priority routes and searching the priority route in reference to the replaceable instruction table(S204). Dependence relation is changed by replacing the found instruction to reduce the dependence with a replaceable instruction(S206). The dependence graph is reformed for the changed loop code and a routine is returned to a first stage(S208). The routine is terminated when the instruction to reduce the dependence is not found in the priority route.

Description

Method of reducing data dependence for software pipelining

1 is an illustration of the lowest loop of the fast Fourier transform algorithm C source code,

FIG. 2 is a diagram illustrating machine language generated by compiling the code of FIG. 1 with a representative StarCore commercial compiler among multi-issue DSPs; FIG.

3 is a view showing the highest priority path generated when the dependency graph of the machine word shown in FIG.

4A to 4C illustrate a procedure of removing a highest priority path by cloning for the loop illustrated in FIGS.

5 is an illustration of one of the lowest loops of the half-rate GSM algorithm C source code,

FIG. 6 is a diagram illustrating machine language generated by compiling the code of FIG. 5 with a representative StarCore commercial compiler among multi-issue DSPs; FIG.

FIG. 7 is a diagram illustrating a highest priority path generated when a dependency graph of the machine word shown in FIG. 6 is drawn;

8A to 8C illustrate a procedure of reducing the highest priority path by demantling for the loops illustrated in FIGS.

9 is a flowchart showing the overall procedure for applying the present invention;

10 illustrates alternative instructions used to apply the present invention.

The present invention relates to a method for improving the performance of a pipelining loop of a digital signal processor (DSP), and more particularly, by reducing the length of the highest priority path on a data dependency graph before applying software pipelining to a DSP. A method of improving the performance of a loop by mitigating dependencies.

In the electronic calculator structure, the CPU generally performs arithmetic operations and predetermined operations by using data stored in a memory. The CPU does not perform a predetermined operation by directly using data stored in a memory, but performs a predetermined operation by using data recorded in a register connected to the CPU. That is, in order for the CPU to use the data stored in the memory, the process of writing the data stored in the memory to a register must be preceded. In addition, the CPU which performs a predetermined operation using the data recorded in the register writes the result data into the register. The result data written to the register is stored in the memory by the given instruction. In this way, the CPU must utilize registers in order to use the data stored in the memory.

A dependency relationship between the instructions of a program is created between instructions using registers and memories of the same name. This is because the result of a specific instruction must be written to a register to determine the order in which the value is available to the next instruction.

Meanwhile, software pipelining, a technique applied to various digital signal processors (DSPs) including multi-issue digital signal processing, is a resource in a range in which instructions between each iteration of a loop do not form a dependency. This technique improves the performance of the loop by nesting the iterations to the extent that is allowed. However, if a register is used again in the next iteration, a dependency relationship is inevitably formed between the two iterations, which acts as a major factor that restricts the software pipelining technique.

In order to solve the above problem, the present inventors have completed the present invention by studying a method for alleviating the dependency relationship between iterations before applying software pipelining. Accordingly, it is an object of the present invention to provide a method that further improves the performance of loops by mitigating the dependencies between pipelining iterations and makes full use of the resources of digital signal processors (especially high performance multi-issue DSPs).

In order to achieve the above object, according to the present invention, a method for mitigating data dependence in loop code of an application program subject to software pipelining,

1) searching all the paths of the data dependency graph created for the machine language for the target loop code, and finding the highest priority path constituting the longest path that determines the execution time of the loop;

2) constructing a replaceable instruction table for the highest priority routes and searching for the highest priority route by referring to the replaceable instruction table, thereby finding an instruction having the smallest priority path length as an instruction that can alleviate dependencies;

3) changing the dependency by replacing the mitigable target instruction found in the step as a replacement instruction.

In addition, the present invention further includes a step of reconstructing the dependency graph with respect to the loop code changed in step 3), and then returning to the first step (ie, step 1) again and repeating the subsequent steps. It features. In step 2), if there is no command that can alleviate the dependency on the highest priority path, the subsequent procedure is terminated.

In step 3), in order to find the instruction having the smallest priority path length, it is preferable to determine the instruction having the greatest (originally the priority path length) minus the (reconstruction priority path length) = (gain) as the final mitigable instruction.

Step 2) includes selecting a set of semantically identical instructions according to a structure of an instruction set of a digital signal processor performing pipelining at the time of constructing the replaceable instruction table, and configuring each of the sets. Determining the increase and decrease of the replacement command according to the interrelationship of the instructions, and reflecting the gain on the resource according to the increase and decrease magnitude in the gain size calculation.

Alternatively, in sequentially searching the highest priority paths according to the replaceable instruction table in step 2), all the paths including the corresponding instructions are recorded together at each time point in which they are searched, thereby replacing the final mitigation instruction with the replacement instruction and relying on the dependency relationship. In the case of mitigating a reaction effect that increases the length of another path at the time of mitigation, it can be reflected in the gain calculation for the highest priority path selection.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 to 3 illustrate the object of the software pipelining preprocessing method for multi-issue digital signal processing, that is, the data dependency mitigation method, according to the present invention. FIG. 1 illustrates the lowest loop of the source code of the fast Fourier transform algorithm written in C. FIG. 2 illustrates a machine language generated by compiling the source code of FIG. 1 with a representative StarCore commercial compiler among multi-issue DSPs, and FIG. 3 is generated when a dependency graph of the machine language illustrated in FIG. 2 is drawn. The highest priority path is shown. 4A to 4C illustrate a process of reducing the highest priority path for the fast Fourier transform algorithm code of FIG. 1 using cloning, which is a feature of the pipelining preprocessing method according to the present invention.

5 illustrates one of the lowest loops of a half-rate GSM algorithm source code written in C, and FIG. 6 compiles the code of FIG. 5 into a representative Starcore commercial compiler among multi-issue DSPs. The generated machine word is shown, and FIG. 7 shows the highest priority path generated when the dependency graph of the machine word shown in FIG. 6 is drawn. 8A to 8C illustrate a procedure of reducing the highest priority path by the dismantling method for the half-rate GSM code illustrated in FIGS. 5 to 7.

Hereinafter, a process of reducing the first priority path size in order to realize the data dependency method according to the present invention with respect to the source code illustrated in FIGS. 1 and 5 will be described. This process is performed in the order of FIG. It demonstrates with reference to FIG.

First, a dependency graph is constructed for the machine language of FIG. The highest priority path as shown in FIG. 3 is found based on the dependency graph formed through the machine words of FIGS. 2 and 6 (S200).

Next, among the instructions constituting the highest priority path, instructions that can replace the dependency configuration with a relaxed instruction are searched in comparison with the replacement instruction table (see FIG. 10) (step S202). If there is no mitigable instruction in the top path, the process ends.

Of each of the mitigable instructions, the instruction with the smallest priority path length reconstructed from the dependency graph constructed when the instruction is replaced with the replacement instruction table, that is, the instruction with the highest gain (originally the highest priority path length minus the reconstruction highest path length) Select to relax command (step S204). This will be explained in detail later.

The selected final relaxation instruction is replaced with a replacement instruction to change the dependency to the desired shape (step S206). In this case, the semantic homogeneity of the entire loop code is maintained. Cloning associated with this will be described in detail with reference to FIG. 4 and dismantling through FIG. 8.

After reconstructing the dependency graph for the changed loop code, the process returns to step S200 and repeats it (step S208).

Now, with reference to the drawings will be described in detail for each of the above-described practical example. First, a description is given of the first priority path reduction process using the cloning technique. Cloning is a technique that removes the highest priority path by changing the register name to another available register if it is true or reverse dependent. At this time, in order to maintain the semantic identity of the loop code, the existing register value must be copied to the new register in the code block before the loop starts.

Assume that the high-performance multi-issue DSP "starcore 1400" operates the machine language illustrated in FIG. The StarCore 1400 can run six instructions at a time, which consists of four Arithmetic Logical Unit (ALU) instructions and two Address Generation Unit instructions. Using these six units as much as possible is the key to improving the performance of your computer.

In the machine language of FIG. 2, the data dependency relation related to the highest priority path is as follows. Commands 1 and 2 of d3 and d4 are used in command 3. Instruction 3 d5 is used in instruction 6 and instruction 7 d5 is used in instruction 8. The d5 of instruction 8 is finally stored at memory address r1 in instruction 9. This dependent path consists of (1, 2) → (3) → (6) → (7) → (8) → (9), and the length of the path is 6 plus the execution time of each instruction. The length of the longest highest priority path in the loop of FIG. 2 is 6, which is represented by the dependency graph in FIG. In FIG. 4A, a command corresponding to the highest priority path is illustrated.

Sequentially searches the commands that make up the highest priority path and finds a mitigable target command that can reduce the path. At this time, use the preconfigured replacement command table. The table is shown in part in FIG. 10, which is configured differently according to the instruction set structure of the multi-issue DSP. The table of FIG. 10 shows some instructions configured according to the instruction set structure of the StarCore 1400. The relaxed target instructions retrieved along the highest priority path of FIG. 3 may be 1, 2, 6, 7, 9 as compared to FIG. 10.

In case of instruction 1, if change like move.w (r10) + n0, d3, dependency between instructions 1 and 9 composed of r1 is changed. As a result, the highest priority path of FIG. 3 is changed from command 3 to 9 as shown in FIG. 4C. The highest priority path of 3 → 9 to be reconstructed has gain 2 as the reconstruction length 4 from the original length 6. In case of 2, 6, and 7, there is no benefit from the dependency that is changed even if the replacement instruction is replaced. In case of 9, one additional command can satisfy gain 2. However, there is a resource overhead used by one additional instruction, so if the gains are the same, the mitigating instruction 1 is given priority.

In FIG. 4B, a process of changing the last mitigation instruction found among the mitigable target instructions into a replacement instruction is illustrated. Changing instruction 1 move.w (r1), d3 to move.w (r10) + n0, d3 removes the dependency relationship by r1 between instruction 1 and instruction 9, changing the top priority path. In order to maintain the semantic identity of the loop code while inserting the replacement instruction, proceed as follows. Copy r1 to r10 register that can be used in the block before loop code, and allocate long size 2 to basic offset register n0 to fill the data change size gap between 1st move.w and 9th move.l instruction. It is added to the replacement register of the replacement instruction.

The reconstruction of the dependency graph for the loop code after the above process is illustrated in FIG. 4C. The priority path has been changed from 3 → 6 → 7 → 8 → 9 and the length has been reduced to 4, reducing the length by 2 for each iteration of the loop code. Assuming that the loop has 10,000 iterations, we have improved 67% of the total execution time of the loop code.

The above procedure is repeated for the reconstructed dependency graph, and the corresponding procedure of the present invention is performed for all the mitigable instructions.

Next, as another example, the first priority path reduction process using the demantling technique will be described. Demantering is a technique to reduce the priority path in case of inverse or output dependence by separating the synthesis instruction into general instructions and changing the register name to another available register. In this case, in order to maintain the semantic identity of the loop code, the general instructions are changed into a plurality of instructions having the same function as the synthesis instructions.

Assume that the machine language of FIG. 6 is operated on the StarCore 1400, a high performance multi-issue DSP. The dependency relationship related to the highest priority path in the machine word of FIG. 6 is as follows. Instruction 2 d10 is used in instruction 3. The command d10 of command 3 is used in command 5 and the command d10 of command 7 is used in command 8. The d10 of the instruction 8 is finally stored in the memory address r4 in the instruction 9. This dependent path consists of (2) → (3) → (5) → (7) → (8) → (9), and the path length is 6 plus the execution time of each instruction. The length of the longest highest priority path in the loop of FIG. 6 is 6, which is represented by the dependency graph in FIG. An instruction corresponding to the highest priority path is shown in FIG. 8A.

Sequentially searches the commands that make up the highest priority path and finds a mitigable target command that can reduce the path. At this time, use the preconfigured replacement command table. This replacement instruction table is shown in part in FIG. 10, which is configured differently according to the instruction set structure of the multi-issue DSP. The table of FIG. 10 shows some instructions configured according to the instruction set structure of the StarCore 1400. The mitigable target instructions retrieved along the highest priority path of FIG. 7 are 3, 5, 7, 8, and 9 compared to FIG.

For command 7, mac is replaced by mpy d3, d12, d11; If add d11, d10, d11, and so on, the dependency between instructions 2 and 9 composed of d10 is changed. As a result, the highest priority path of FIG. 7 is changed from command 2 to command 7 as shown in FIG. 8C. The highest priority path of 2 → 7 to be reconstructed has a gain of 3 as the reconstruction length 3 from the original length 6. In the case of 3, 5, and 9, there is no benefit from the dependency that is changed even if the replacement instruction is replaced. In case of 8, gain 1 can be satisfied by separating the synthesis instruction and removing the path from 9 to 2 as in the case of instruction 7. However, since the gain is the highest in instruction 7, the final mitigation instruction is determined as seven.

8B illustrates a process of changing the final mitigation instruction found among the mitigable target instructions into a replacement instruction. D11, which is used to separate instruction 7 into normal instructions, is one of the registers available in the loop as a result of dataflow analysis. Changing the value of d10 to d11 removes the dependency relationship by d10 between commands 2 and 9, changing the top priority path.

The reconstruction of the dependency graph for the loop code after the above process is illustrated in FIG. 8C. The priority path has been changed from 2 → 3 → 5 → 7 and the length has been reduced to 3, reducing the length by 3 for each iteration of the loop code. Assuming that the loop has 10,000 iterations, the total execution time of that loop is twice as fast.

The above procedure is repeated for the reconstructed dependency graph, and the corresponding procedure of the present invention is performed for all the mitigable instructions.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the present invention is not limited to the specific embodiments of the present invention without departing from the spirit of the present invention as claimed in the claims. Anyone of ordinary skill in the art can make various modifications, and such changes are within the scope of the claims.

The present invention proposes a method for efficiently improving the performance of a loop by reducing the length of the priority path on the dependency graph as a preprocessing technique supporting software pipelining. To this end, the mitigation targets on the highest priority path are sequentially searched for, and the performance improvement gains are calculated from the targets. This improves loop performance and increases resource utilization of multi-issue DSPs.

Claims (9)

As a method of mitigating data dependence in loop code of an application that is subject to software pipelining, 1) searching all the paths of the data dependency graph created for the machine language for the target loop code, and finding the highest priority path constituting the longest path that determines the execution time of the loop; 2) constructing a replaceable instruction table for the highest priority routes and searching for the highest priority route by referring to the replaceable instruction table, thereby finding an instruction having the smallest priority path length as an instruction that can alleviate dependencies; 3) changing the dependency by replacing the mitigable target instruction found in the step as a replacement instruction. The method of claim 1, Reconstructing the dependency graph for the loop code changed in step 3) is further included.  And returning to the first step (i.e., step 1)) and repeating the subsequent steps. The method of claim 1, If there is no instruction that can reduce the dependence on the priority path in the step 2), the step further comprises the step of terminating the data dependency of software pipelining. The method according to claim 1 or 2, In step 3), in finding the instruction having the smallest priority path length, the method having the greatest gain on the path length is determined as the final mitigable instruction. The method of claim 4, wherein the gain is (Gain) = (originally highest priority path length)-(reconstruction highest priority path length). The method of claim 4, wherein in the step 2), when the first priority path is sequentially searched according to the replaceable instruction table, If all the paths containing the instruction are recorded together at each point in time that is retrieved, replacing the final mitigation instruction with a replacement instruction produces a reaction effect that increases the length of the other path at the point of mitigation of the dependency relationship. A method for mitigating data dependency of software pipelining, which is reflected in the gain calculation. The method of claim 4, wherein step 2) Selecting a set of semantically identical instructions according to a structure of an instruction set of a digital signal processor performing pipelining at the time of constructing the replaceable instruction table; Determining the increase or decrease of the replacement command according to the mutual relationship of each command constituting the set, And reflecting the gains about the resource in the gain magnitude calculation according to the increase and decrease magnitudes. The method of claim 1, wherein step 2) Selecting a set of semantically identical instructions according to a structure of an instruction set of a digital signal processor performing pipelining at the time of constructing the replaceable instruction table; And determining the increase or decrease of the replacement instruction according to the interrelationship of each instruction constituting the set. The method of claim 1, wherein in the step 2), if the first priority path is sequentially searched according to the replaceable instruction table, By recording all the paths that contain the command at each point in time that is retrieved, the highest priority path selection reflects the case in which the final relaxation command is replaced with a replacement command to produce a reaction effect that increases the other path lengths at the time of easing the dependency relationship. A method for mitigating data dependence of software pipelining, characterized in that.

Images