KR20120040630A - Reconfigurable processor and method for processing loop having memory dependency - Google Patents

Abstract

PURPOSE: A reconfigurable processor to handle a memory dependent loop and a method thereof are provided to analyze the dependency between memory access commands, thereby allocating the commands to a plurality of processing elements based on the analyzed result. CONSTITUTION: An extracting unit(140) extracts an operation trace from a simulation result. A scheduler(150) analyzes the memory dependency between commands of iterations based on a corresponding trace to a memory access command out of the operation traces. A simulation unit(130) simulates the commands. The scheduler analyzes the memory dependency between the commands of iterations which exist in a generated iteration window.

Description

RECONFIGURABLE PROCESSOR AND METHOD FOR PROCESSING LOOP HAVING MEMORY DEPENDENCY}

When executing operations on iterations in parallel, techniques are involved in assigning instructions to multiple processing elements so that the operations can be executed correctly.

Reconfigurable architecture refers to an architecture that can change the hardware configuration of a computing device to perform a task to be optimized for each task.

If a task is processed only in hardware, the fixed hardware function makes it difficult to process it efficiently if a small change is made to the task. In addition, it is possible to process a job by changing only the software in accordance with the contents of the job if the job is done only in software, but it is slower than the hardware process.

Reconfigurable architectures can meet all of these hardware / software advantages. In particular, in the field of digital signal processing where the same operation is performed repeatedly, such a reconfigurable architecture attracts much attention.

On the other hand, the digital signal processing process generally includes a plurality of loop operation processes in which the same operation is repeated due to its signal processing characteristics. In general, loop level parallelism (LLP) is widely used to speed up loop operations. Software pipelining is typical of such LLP.

Software pipelining uses the principle that even operations belonging to different iterations can be processed simultaneously without dependencies between the iterations. This software pipelining can be combined with reconfigurable arrays for better performance. For example, it is possible for parallelizable operations to be processed simultaneously in each processing unit constituting a reconfigurable array.

Recently, there is an increasing need for research on a technique for allocating instructions to a plurality of processing elements such that the instruction of a memory-dependent loop is correctly calculated in executing pipelining.

It relates to a reconfigurable processor that can reduce erroneous operations by analyzing dependencies between memory access instructions and assigning instructions to multiple processing elements based on the analyzed results.

A reconfigurable processor for processing a memory dependent loop according to an embodiment of the present invention is included in iterations based on an extractor for extracting a computational trace from a simulation result and a trace corresponding to a memory access instruction among the computational traces. It includes a scheduler that analyzes the memory dependencies between the issued instructions.

It may further include a simulation unit for simulating the commands.

The scheduler may generate an iteration window corresponding to a processing time of instructions included in one iteration, and analyze a memory dependency relationship between instructions included in the iteration existing in the generated iteration window.

The scheduler may calculate a minimum iteration distance (MII) between the iterations based on the analyzed memory dependency.

The scheduler may assign instructions to processing elements while increasing an iteration distance (II) from the computed MII based on the analyzed memory dependency.

And said operation trace comprises at least one of a register address, a value stored in a register, a memory address, and a value stored in memory.

A method of processing a memory-dependent loop according to an embodiment of the present invention includes extracting an operation trace from a simulation result, and based on a trace corresponding to a memory access instruction among the operation traces, between instructions included in the iterations. Analyzing the memory dependencies.

The method may further include simulating the instructions.

The analyzing may include generating an iteration window corresponding to a processing time of instructions included in one iteration, and analyzing a memory dependency relationship between instructions included in the iteration existing in the generated iteration window. have.

The method may further include calculating a minimum iteration distance (MII) between the iterations based on the analyzed memory dependency relationship.

The method may further include allocating processing elements in consideration of the analyzed memory dependency while increasing an iteration distance (II) value from the calculated MII based on the analyzed memory dependency.

The operation trace may include at least one of a register address, a value stored in a register, a memory address, and a value stored in a memory.

According to the present disclosure, by extracting the memory dependency between the instructions from the operation trace obtained through profiling, and assigning the instructions contained in the iteration to a plurality of processing elements based on the extracted memory dependency, The accuracy of calculations can be improved than when not considered.

In addition, it is possible to reduce dependency analysis time by analyzing dependency relationships between memory access commands using an iteration window.

1 is a view for explaining a reconfigurable processor associated with an embodiment of the present invention.
2 is a view for explaining an iteration window according to an embodiment of the present invention.
3A and 3B are diagrams for explaining MII.
4 is a flowchart illustrating a control method of a reconfigurable processor according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the specific contents for carrying out the invention.

1 is a view for explaining a reconfigurable processor associated with an embodiment of the present invention.

Referring to FIG. 1, the reconfigurable processor 100 includes a reconfigurable array 110, a memory 120, a simulation unit 130, an extractor 140, and a scheduler 150.

Hereinafter, iteration means the execution of each loop when the loop is executed several times. For example, if a loop is executed three times, the first execution of the loop may be referred to as the first iteration, the second execution of the loop may be referred to as the second iteration, and the third execution of the loop may be referred to as the third iteration. As instructions belonging to the iteration are mapped to different processing elements and each processing element operates simultaneously, the instructions can be processed in parallel. Accordingly, the computation speed can be improved.

The reconfigurable processor 100 may be driven in a coarse-grained array (CGA) mode, a very long instruction word (VLIW) mode, or the like. For example, the reconfigurable processor 100 may process a loop operation in the CGA mode, and may process a general operation or a loop operation in the VLIW mode. However, loop operation can be performed in VLIW mode, but is less efficient than loop operation in CGA mode. For example, when one program is executed, the reconfigurable processor 100 may be driven alternately between the CGA mode and the VLIW mode.

Reconfigurable array 110 includes register file 111 and a number of processing elements (PEs) 112. The reconfigurable array 110 may change the hardware configuration to perform an optimal operation. For example, the reconfigurable array 110 may change a connection state between a plurality of processing elements according to the type of operation.

The register file 111 is used for data transfer between the processing elements 112 or stores various data necessary for executing an instruction. For example, each processing element 112 may access the register file 111 to read or write data used in executing instructions. However, since not all processing elements 112 are connected to each other, in the case of a specific processing element, it may be via another processing element to access the register file 11.

Processing elements 112 may execute the assigned instructions. The connection state and the operation order of the processing elements 112 may be changed according to the task to be processed.

The memory 120 may store information necessary for processing such as information about a connection state between the processing elements 112, instructions, and the like, and result information of the processing. For example, the memory 120 may store data to be processed. You can either save or save the processing results. As another example, the memory 120 may store information necessary for driving the reconfigurable processor 100, connection state information of the reconfigurable array, and information on a method of operating the reconfigurable array.

The simulation unit 130 may execute a simulation by applying instructions to be executed in the processing element to a test file. For example, the simulation unit 130 may execute a simulation of processing a test file (eg, an MP3 file, a video file, etc.) by using commands.

The extraction unit 140 may extract an operation trace from the simulation result executed by the simulation unit 130. This is also called profiling. The operation trace is data in which information about an instruction executed during a simulation is recorded in chronological order, and the recorded data may be values of variables at the moment of execution of each instruction. For example, the operation trace may include a register address, a value stored in a register, a memory address, a value stored in a memory, and the like.

The scheduler 150 may analyze the memory dependency between the instructions based on the trace ('traced variable value') corresponding to the memory access instruction among the operation traces. If there is an instruction that accesses the same memory among the instructions included in each iteration, there is a memory dependency between the instructions. In this case, the instructions must be processed serially for correct operation. The memory access command may refer to a command for storing data to or reading data from the memory 120. For example:

k iteration:

A: ld _i r20  <-M [0x50]

B: add r2  <- r4  + r5

C: st _i M [0x100] <- r8

D: sub r1  <- r4  - r5

E: st _i M [0x1000] <- r10

k + 1 iteration:

A: ld _i r20  <-M [0x100]

B: add r2  <- r4  + r5

C: st _i M [0x150] <- r8

D: sub r1  <- r4  - r5

E: st _i M [0x1000] <- r10

Here, ld is a load command, add is an addition command, st is a store command, and sub is a subtraction command. The memory access command means a command including M [].

The register (r) dependency analysis can be easily seen by comparing only the name of the register. On the other hand, memory dependency analysis can be found only by comparing the address values (eg, '0x100', '0x150') of the memory stored in the register. Thus, memory dependency analysis is relatively difficult compared to register dependency analysis.

The operation trace is a register address ('r1, r2, r4, r5, r8, r10, r20'), the value stored in the register, or the memory address or memory corresponding to the memory access instruction contained in the kth and k + 1th iterations. It can contain values stored in addresses.

The scheduler 150 may analyze the dependency relationship between the instructions based on the trace corresponding to the memory access instruction. For example, when the address value of the memory corresponding to the memory access command is the same, the scheduler 150 may determine that a memory dependency relationship exists between the corresponding memory access commands. For example, since the memory address value '0X100' of the k-th iteration C and the memory address value '0x100' of the k + 1 iteration A are the same, the scheduler 150 performs the k-th iteration C and the k + 1st iteration. It may be determined that iteration A has a dependency. In another example, when the value stored in M [0X100] of the k-th iteration C and the value stored in M [0X100] of the k + 1 iteration A are the same, the scheduler 150 performs the k-th iteration C and k. It can be determined that the + 1th iteration A has a dependency relationship. The scheduler 150 may analyze the above dependencies based on the simulation result. Although the process of determining the memory dependency relationship between the k-th iteration and the k + 1 iterations has been described, the scheduler 150 performs the k-th iteration and the k + 2-th iteration, the k-th iteration and the k + 3-th iteration. It also determines the memory dependency between migrations.

The scheduler 150 may calculate a minimum iteration distance (MII) based on the memory dependency.

The scheduler 150 may allocate instructions to the processing elements in consideration of the analyzed memory dependency while increasing the II value from the calculated MII. For example, the scheduler 150 may allocate instructions to processing elements in consideration of the analyzed memory dependency while increasing the iteration distance (II) value by 1 from MII. This is also known as trial-and-error. However, the trial and error method is only one embodiment, and another method of calculating the II value from the calculated MII may be used.

The scheduler 150 may generate an iteration window corresponding to the processing time of the instructions included in one iteration, and analyze a dependency relationship between the instructions included in the iterations present in the generated iteration window. The scheduler 150 corresponds to a processing time of instructions included in one iteration. Create an iteration window. The scheduler 150 may analyze the dependency relationship between the commands with respect to sequentially inputted iterations.

The scheduler 150 analyzes dependency relationships between memory access commands using an iteration window, thereby reducing dependency analysis time. That is, by using the iteration window, the dependency relationship between the commands included in the iterations that do not need to be analyzed may not be analyzed.

2 is a view for explaining an iteration window according to an embodiment of the present invention.

In this embodiment, iteration is assumed to be inputted every cycle (II = 1), and the processing time of an instruction included in one iteration is 10 cycles.

1 and 2, the iteration window 200 may be generated with a size equal to or larger than a processing time of an instruction included in one iteration. For example, since the processing time of instructions included in one iteration is 10 cycles, the iteration window 200 may include 10 iterations corresponding to 10 cycles, or may include 10 or more iterations. Can be generated. It takes 10 cycles to enter 10 iterations.

The scheduler 150 may analyze the dependency relationship between the commands included in the iterations included in the iteration window. For example, between the currently entered iteration ('first iteration') and the input iteration ('the eleventh iteration') that exceeds the processing time ('10 cycles') of the commands contained in the currently entered iteration Dependencies do not need to be analyzed. The reason is that the first iteration and the eleventh iteration are not computed at the same time ('parallel'), but rather sequentially ('serial'). That is, after the first iteration is calculated, the eleventh iteration is calculated. Accordingly, the size of the iteration window may be set equal to or larger than the size corresponding to the processing time of the instructions included in one iteration.

The scheduler 150 may analyze the instructions to be executed in the reconfigurable array 110 and assign the instructions to the plurality of processing elements 112 based on the analysis results.

The scheduler 150 may calculate the MII of iterations. The scheduler 150 may assign an instruction to the processing elements using the analyzed memory dependency while increasing the iteration distance (II) from the calculated minimum iteration distance (MII).

3A and 3B are diagrams for explaining MII.

3A is a diagram illustrating a case where MII is 1, and A, B, C, D, and E indicate an instruction.

Referring to FIG. 3A, the scheduler 150 may allocate instructions to a processing element in consideration of the analyzed memory dependency while increasing an iteration distance (II) value by 1 from a minimum iteration distance (MII). For example, if there is a dependency relationship between A of the first iteration 200a and B of the second iteration 210a, the scheduler 150 determines that the B command of the second iteration 210a is the first iteration. The MII value may be calculated to be executed after the A instruction of the migration 200a is executed. The scheduler 150 may then assign instructions to the processing element taking into account the resolved memory dependency while increasing the II value from the computed MII.

3B is a diagram illustrating a case where MII is 3, and A, B, C, D, and E indicate an instruction.

Referring to FIG. 3B, the scheduler 150 may allocate instructions to a processing element in consideration of the analyzed memory dependency while increasing an iteration distance (II) by 1 from a minimum iteration distance (MII). For example, II may be increased by 1 from 3, the MII value. For example, if there is a dependency relationship between D of the first iteration 200a and B of the second iteration 210a, the scheduler 150 determines that the B command of the second iteration 210a is the first iteration. The MII value may be calculated to be executed after the D instruction of the migration 200a is executed. The scheduler 150 may allocate instructions to the processing element in consideration of the analyzed memory dependency while increasing the II value from the calculated MII.

4 is a flowchart illustrating a control method of a reconfigurable processor according to an embodiment of the present invention.

Referring to FIG. 4, simulations are performed by applying instructions to be executed on a plurality of processing elements to a test file (400). The operation trace is extracted from the simulated result (410). Based on the trace corresponding to the memory access instruction among the operation traces, the memory dependency relation between the instructions included in the iterations is analyzed (420). For example, an iteration window corresponding to a processing time of instructions included in one iteration may be generated, and dependency relationships between the commands included in the iterations present in the generated iteration window may be analyzed. A minimum iteration distance (MII) between the iterations is calculated based on the analyzed memory dependency (430). Instructions 440 are allocated to the processing elements in consideration of the memory dependency while increasing the II value from the minimum iteration distance (MII) calculated based on the analyzed memory dependency.

The control method of the reconfigurable processor can improve the accuracy of the operation by assigning iterations to the plurality of processing elements based on the dependencies between the memory access instructions.

In addition, the control method of the reconfigurable processor may reduce dependency analysis time by analyzing dependency relationships between memory access commands using an iteration window corresponding to a processing time of one iteration.

The embodiments described may be constructed by selectively combining all or a part of each embodiment so that various modifications can be made.

It should also be noted that the embodiments are for explanation purposes only, and not for the purpose of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Further, according to an embodiment of the present invention, the above-described method can be implemented as a code that can be read by a processor on a medium on which the program is recorded. Examples of processor-readable media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may be implemented in the form of a carrier wave (for example, transmission over the Internet). Include.

Claims (12)

An extraction unit for extracting a calculation trace from the simulation result; And
And a scheduler for analyzing a memory dependency between instructions included in the iterations based on a trace corresponding to a memory access instruction among the operation traces.
The method of claim 1,
And a simulation unit for simulating the instructions.
The method of claim 1,
The scheduler,
Processes a memory-dependent loop that generates an iteration window corresponding to the processing time of instructions included in one iteration, and analyzes the memory dependency between instructions included in the iterations present in the generated iteration window. Reconfigurable processor for
The method of claim 1,
The scheduler,
A reconfigurable processor for processing a memory dependent loop that calculates a minimum iteration distance (MII) between the iterations based on the analyzed memory dependency.
The method of claim 4, wherein
The scheduler,
A reconfigurable processor for processing a memory dependent loop that allocates instructions to processing elements while increasing an iteration distance from the computed MII based on the analyzed memory dependency.
The method of claim 1,
And said operation trace comprises at least one of a register address, a value stored in a register, a memory address, and a value stored in memory.
Extracting a computational trace from the simulation result; And
Analyzing a memory dependency between instructions included in the iterations based on a trace corresponding to a memory access instruction among the operation traces.
The method of claim 7, wherein
And simulating the instructions.
The method of claim 7, wherein
The analyzing step
Processing of a memory-dependent loop that generates an iteration window corresponding to the processing time of instructions included in one iteration, and analyzes the memory dependency between instructions included in the iterations present in the generated iteration window. Way.
The method of claim 7, wherein
Computing a minimum iteration distance (MII) between the iterations based on the analyzed memory dependency relationship.
The method of claim 10,
And assigning to processing elements in consideration of the analyzed memory dependency while increasing an iteration distance (II) value from the calculated MII based on the analyzed memory dependency. Treatment method.
The method of claim 7, wherein
And wherein said operation trace comprises at least one of a register address, a value stored in a register, a memory address, and a value stored in memory.

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