JP2881023B2 - Instruction buffer configuration method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction buffer configuration system provided in a computer using a pipeline control system.

(Prior Art) The pipe-Iran control method is a method in which an instruction executed by a central processing unit of a computer is divided into a plurality of stages, and each of the divided stages is processed in parallel by a separate processing circuit. With such a pipeline control method, the data processing time of the central processing unit can be reduced. By the way, the central processing unit of the pipeline control system is provided with an instruction buffer for prefetching an instruction in order to improve an instruction reading speed.

FIG. 2 is a block diagram showing a conventional instruction buffer configuration method.

FIG. 1 shows a main storage device 1 and a central processing unit 2.

The main storage device 1 is composed of a random access memory and stores an instruction sequence.

The central processing unit 2 executes the instruction sequence. The central processing unit 2 is provided with instruction buffers 41 to 44 and an instruction fetch control unit 45.

The instruction buffers 41 to 44 are composed of random access memories, and perform prefetching of instructions. The size of each of these instruction buffers 41 to 44 is 8 bytes.
The instruction fetch control unit 45 controls the transfer of an instruction sequence to the instruction buffers 41 to 44.

The instruction buffers 41 and 42 are used as a pair of seesaw buffers. That is, when the empty state of one of the instruction buffers is detected, the instruction buffer control unit 45 reads the instruction sequence from the main storage device 1 into the empty instruction buffer. The instruction buffers 43 and 44 are also used as a pair of seesaw buffers, like the instruction buffers 41 and 42.

One of the two sets of the instruction buffers 41 and 42 and the instruction buffers 43 and 44 is used to store the currently executed instruction sequence, and the other set is a branch for executing the conditional branch instruction. Used to store the previous instruction sequence. The instructions stored in the instruction buffers 41 to 44 are divided into a plurality of stages and sent to the instruction pipeline control unit 3.

The instruction pipeline control unit 3 includes a D stage control unit 4
X stage controller 5, A stage controller 6, E
And a stage control unit 7.

 D stage control unit 4 performs instruction decoding.

X stage control unit 5 performs address calculation. That is, for the branch instruction, the address of the branch destination is calculated. For an instruction having an operand, the address of the operand is calculated.

A stage control unit 6 performs prefetching of operands.

E stage control unit 7 performs arithmetic processing on operands.

The instructions stored in the instruction buffers 41 to 4 are executed in the order of these stages, and the stages are simultaneously operated to perform pipeline control.

FIG. 5 is a diagram showing an example of the arrangement of instructions on the main storage device.

6 instructions of 4 bytes in length from address 1000 (instructions 01 to 0)
6) are arranged continuously. In addition, six instructions (instructions 11 to 16) having a length of 4 bytes from address 2,000 are continuously arranged. Here, the instructions other than the instruction 02 are instructions that do not involve a branch. These instructions are sequentially executed in ascending order of address, for example, such that instruction 04 is executed after instruction 03.

Instruction 02 is a conditional branch instruction. That is, if a certain condition is satisfied, the instruction at address 2000 (instruction
11) is executed. On the other hand, if a certain condition is not satisfied, the instruction (instruction 03) at the next address is executed as in the other instructions.

FIG. 3 is a time chart when the instruction sequence of the arrangement shown in FIG. 5 is executed from address 1000 in the apparatus of FIG.

 The operation of the conventional example will be described below with reference to FIG.

In the initial state, the instruction buffers 41 and 42 are used for a currently executed instruction sequence. Meanwhile, the instruction buffer
Reference numerals 43 and 44 are used for a branch destination instruction sequence in the case of a conditional branch.

First, when an instruction is executed from the address 1000 in FIG. 5, the instruction fetch control unit 45 executes an instruction sequence (instruction) of 8 bytes from the address 1000 in the main storage device 1 at time T0.
01, 02) are read into the instruction buffer 41. At time T1, since the instruction buffer 42 is empty, the instruction fetch control unit 45 further reads an instruction sequence (instructions 03 and 04) of 8 bytes from address 1008 into the instruction buffer 42. At the same time T1, the instruction 01 at address 1000 read into the instruction buffer 41 is sequentially executed through the D stage, X stage, A stage, and E stage.

At time T3, the instruction buffer 41 becomes empty due to the execution of the instructions 01 and 02 in the D stage. Therefore, the instruction fetch control unit 45 reads an instruction sequence (instructions 05 and 06) of 8 bytes from the address 1010 into the instruction buffer 41. At time T3, the D stage of the instruction 03 starts, and at time T4, the D stage of the instruction 04 starts. Here, since instruction 02 is a conditional branch instruction, X of instruction 02
At time T3 when the stage is executed, the branch destination address 2000 is calculated. At the time T4 following this, the instruction fetch control unit 45 sets the address of the main storage device 1 from 2000 to 8
The instruction sequence (instructions 11 and 12) for bytes is transferred to the instruction buffer 43. Further, at time T5, the instruction fetch control unit 45
The instruction sequence (instructions 13 and 14) of 8 bytes from address 08 is transferred to the instruction buffer 44. On the other hand, at time T5, the E stage of the conditional branch instruction 02 is executed, a certain condition is determined, and it is determined whether or not the branch is taken.

FIG. 3 is a time chart in the case where the branch is taken. At time T6 following T5, the D stage of the instruction 11 at the address 2000 previously read into the instruction buffer 43 at time T4 starts, and from time T7. The D stage of instruction 12 is started. Further, at time T8, the D stage of instructions 11 and 12 has been executed until time T7, so that the instruction buffer 44
Becomes empty, and an 8-byte instruction sequence (instructions 15 and 16) from address 2010 is transferred to the instruction buffer 44. Thereafter, the instruction buffers 43 and 44 are used and instruction fetch is continued until the next branch instruction appears.

As described above, from time T0 to time T5, the instruction buffer 41
And 42 are used to read the currently executing instruction sequence,
The instruction buffers 43 and 44 are used to read the instruction sequence at the branch destination of the conditional branch instruction. After time T6, instruction buffers 43 and 44 are used to read the currently executing instruction sequence.

(Problems to be solved by the invention) However, the above-described conventional technology has the following problems.

That is, in the method described above, only one set of instruction buffers is used while executing instructions other than the conditional branch instruction. That is, two sets of instruction buffers are required only for executing the conditional branch instruction, and there is a problem that the amount of hardware is increased.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an instruction buffer configuration method capable of reducing the amount of hardware while maintaining the performance of pipeline control.

(Means for Solving the Problems) According to an instruction buffer configuration method of the present invention, a storage device for storing a plurality of instruction sequences, an instruction buffer having three surfaces for storing instructions to be executed by pipeline control in advance, and An instruction fetch control unit for transferring an instruction sequence stored in a storage device to the three-sided instruction buffer, wherein the instruction fetch control unit comprises two instruction buffers of the three-sided instruction buffer The instruction sequence currently being executed is transferred to the instruction buffer on the other side, and the instruction sequence at the branch destination of the conditional branch instruction is transferred to the remaining one instruction buffer.

(Operation) In the instruction buffer configuration method of the present invention, the instruction buffer is used for two currently executed instruction strings among the three instruction buffers. On the other hand, the remaining one side is used for the instruction sequence at the branch destination of the conditional branch instruction. Therefore, the instruction buffer that is not used in a state where the conditional branch instruction is not executed can be provided on only one surface, and the amount of hardware can be reduced.

(Embodiment) FIG. 1 is a block diagram of an embodiment of an instruction buffer configuration system according to the present invention.

FIG. 1 shows a main storage device 1 and a central processing unit 2.

The main storage device 1 is similar to the conventional one shown in FIG.
It consists of a random access memory and stores a sequence of instructions.

The central processing unit 2 'executes the instruction sequence. The central processing unit 2 'is provided with instruction buffers 11 to 13 and an instruction fetch control unit 14.

The instruction buffers 11 to 13 are composed of random access memories, and perform prefetching of instructions. The size of each of the instruction buffers 11 to 13 is 8 bytes.
The instruction fetch control unit 14 controls the transfer of an instruction sequence to the instruction buffers 11 to 13.

When the instruction buffer 11 is used to read the currently executed instruction sequence, the instruction buffer 11 is used together with the instruction buffer 12 as a seesaw buffer. At this time, the instruction buffer 13 is used for reading a branch instruction sequence of the conditional branch instruction. When the instruction buffer 13 is used to read a currently executed instruction sequence, the instruction buffer 13 is used as a seesaw buffer together with the instruction buffer 12. At this time, the instruction buffer
Reference numeral 11 is used to read a branch destination instruction sequence of a conditional branch instruction.

The instruction pipeline control unit 3 is, like the conventional one,
It comprises a D stage control unit 4, an X stage control unit 5, an A stage control unit 6, and an E stage control unit 7.

 D stage control section 4 decodes the instruction.

X stage control unit 5 performs address calculation. That is, for the branch instruction, the address of the branch destination is calculated. For an instruction having an operand, the address of the operand is calculated.

A stage control unit 6 performs prefetching of operands.

E stage control unit 7 performs arithmetic processing on operands.

The instructions stored in the instruction buffers 11 to 13 are executed in the order of these stages, and the stages are simultaneously operated to perform pipeline control.

FIG. 4 is a time chart for explaining the operation of FIG.

In this figure, the instruction sequence shown in FIG.
It is a time chart at the time of starting from an address. Less than,
The operation of one embodiment of the present invention will be described with reference to FIG.

In the initial state, it is assumed that the instruction buffer 11 is used for the currently executed instruction sequence and the instruction buffer 12 is used for the branch destination instruction sequence of the conditional branch instruction.

First, when an instruction is executed from the address 1000 in FIG. 5, the instruction fetch control unit 14 fetches an 8-byte instruction sequence (instructions 01 and 02) from the address 1000 in the main storage device 1 at time T0. Read into the instruction buffer 11. At time T1, since the instruction buffer 12 is empty, the instruction fetch control unit 14 reads an instruction sequence (instructions 03 and 04) of 8 bytes from address 1008 into the instruction buffer 12. At the same time T1, the execution of the instruction 01 at the address 1000 read into the memory buffer 11 is started from the D stage. Similarly, instruction 02 at address 1004 from time T2 starts at time T3
The instruction 03 at the address 1008 starts executing from the D stage from the time T4. On the other hand, at the time T3, the instruction buffer 11 becomes empty due to the execution of the instructions 01 and 02 in the D stage, so that the instruction fetch control unit 14 executes the instruction sequence of eight bytes from the address 1010 (the instructions 05 and
06) into the instruction buffer 11. Here, since the instruction 02 is a conditional branch instruction, the branch destination address 2000 is calculated at the time T3 when the X stage of the instruction 02 is executed.
At the subsequent time T4, the instruction fetch control unit 14
Transfers an instruction sequence (instructions 11 and 12) of 8 bytes from the address 2000 to the instruction buffer 13. On the other hand, at time T5,
The E stage of the conditional branch instruction 02 is executed, a certain condition is determined, and it is determined whether or not the branch is taken. 4th
The figure is a time chart in the case where the branch is taken. At time T6 following time T5, the D stage of the instruction 11 of the address 200 previously read into the instruction buffer 13 at time T4 is started, and the instruction is started at time T7. Twelve D stages are started.
When the conditional branch is taken at time T5, the instruction buffer 12 is switched to be used together with the instruction buffer 13. At time T6, an 8-byte instruction string (instructions 13 and 14) from address 2008 is stored in the memory buffer 12. Will be transferred. At time T8, the D stages of instruction 11 and instruction 12
By this time, the instruction buffer 13 becomes empty, and the 8-byte instruction string (instructions 15, 1
6) is transferred to the instruction buffer 13. Thereafter, the instruction buffer 13 and the instruction buffer 12 are used for fetching the currently executed instruction sequence until the next branch instruction appears.

(Effect of the Invention) As described above, according to the instruction buffer configuration method of the present invention, two instruction buffers for three planes are used, and hardware for four planes is conventionally required. On the other hand, an instruction buffer can be constituted by hardware for three surfaces. Further, even when the branch of the conditional branch instruction is taken, the same performance as that of the related art can be obtained, and when the conditional branch instruction is not taken, the same performance can be obtained.
As described above, according to the present invention, it is possible to configure an instruction buffer having the same performance as the conventional one with a smaller amount of hardware than the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an instruction buffer configuration system according to the present invention, FIG. 2 is a block diagram showing a conventional instruction buffer configuration system, and FIG. 3 is a time chart for explaining the operation of FIG. FIG. 4 is a time chart for explaining the operation of FIG. 1, and FIG. 5 is an instruction arrangement diagram on the main storage device. DESCRIPTION OF SYMBOLS 1 ... Main storage device, 2 '... Central processing unit, 3 ... Instruction pipeline control unit, 4 ... D stage control unit, 5 ... X stage control unit, 6 ... A stage control unit, 7 ... E stage control unit, 11 , 12, 13 ... instruction buffer, 14 ... instruction fetch control unit.

Claims (1)

(57) [Claims] 1. A storage device for storing a plurality of instruction sequences, an instruction buffer having three surfaces for storing instructions to be executed by pipeline control in advance, and an instruction sequence stored in the storage device being read from the three surfaces. An instruction fetch control unit for transferring the currently executed instruction sequence to two instruction buffers of the three instruction buffers, and An instruction buffer configuration method, wherein an instruction sequence at a branch destination of a conditional branch instruction is transferred to an instruction buffer on a side.