JPH01131920A - Parallel-parallel conversion circuit - Google Patents

Abstract

PURPOSE:To perform parallel-parallel conversion at high speed by taking out (n) bits of constant length from an arbitrary position in a continuous bit string to be inputted in unit of (m) bits by one clock. CONSTITUTION:Two pairs of input registers 101 and 102 having (m) bit width which latch data inputted in parallel in unit of (m) ((m) is constant >=2) bits, a shift circuit possible to take out (n) bits (m>=n) by applying arbitrary bit shift on the values of the input registers 101 and 102, a shift number integrator 107 to integrate the number of shifts, and a latch pulse generation circuit 106 to generate the latch pulses of the input registers 101 and 102 based on the detected value of the shift number integrator 107 are provided. In such a case, no conversion of parallel data to digital data is performed, the data is handled as the parallel data as it is. In such a way, it is possible to take out the data of (n) bits, especially the data extending over a word boundary from the arbitrary position in the data inputted in unit of (m) blocks at high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit that performs parallel-to-parallel conversion, and particularly relates to a method for extracting fixed n bits from arbitrary points in a continuous bit string input in units of m bits. . The present invention is particularly effective for variable length code decoding circuits in change point detection and decoding in encoding based on MH and MR systems.

[Conventional technology]

In the fields of image processing and communications, continuous data is usually handled in parallel in units of m bits (m is a constant). For example, an 8-bit computer processes data in bytes, and a 16-bit computer processes data in 2-byte units.

- A collection of bits that can be handled at a time is called a word. Here, a specific pattern (
Consider a case where an attempt is made to detect a length of n bits (where n is a constant). This pattern may span between one word and the next. Therefore, in order to detect this pattern, it is necessary to extract fixed n bits from arbitrary points among continuous bits input in units of m bits.

This kind of operation is performed in image processing when the color in the data of a continuous binary image changes (the bit changes from "0" to "1" or from "1" to "0"). When detecting bit positions, when decoding variable length code strings encoded using encoding methods such as MH/MR, when searching for MH/MR encoded directional codeword system ELO codes, etc. be. Furthermore, in the field of communications, it is used to search for the start flag of the next packet when communications are out of synchronization.

In such cases, conventionally the parallel input data is
The operation involved converting to serial data, latching the serial data into a shift register, and converting it back to parallel data.

FIG. 6 shows a block diagram of the conventional example, and FIG. 7 shows an example of the operation of this conventional example. The data shown in FIG. 2 is used as an example of the input bit string. Here, it is assumed that the data for both input and output is 8 bits.

In FIG. 6, a shift register 601 sends data input in parallel using a signal from a latch pulse generator 603 to an output register 602 bit by bit using a shift signal from a shift number accumulating circuit 604. The shift number integration circuit 604 outputs shift signals equal to the number of shifts inputted from the outside. This shift signal is output to the output register 60.
Also given to 2. The value entered into the output register 602 is
It becomes the output data as is. The shift number integration circuit 604 integrates the number of shifts input from the outside, and this is 8.
When this happens, the latch pulse generator 603 is notified. In response to this, the latch pulse generator 603 outputs the shift register 6.
01 sends a latch signal to.

In this example, consider the case where 8 consecutive bits are extracted from the 8th bit counting from the beginning of input data. When the first byte of data is in the shift register 601, it takes eight clocks to input it into the output register 602 (the state shown in the first row of FIG. 7). In this state, the settlement value in the shift number accumulating circuit 604 becomes 8, so the second byte of data is latched into the shift register 601. Furthermore, it is necessary to shift another 7 bits in order to extract consecutive 8 bits from the 8th bit of this data. This takes 7 clocks. In this example, it can be seen that it takes 15 clocks to perform the desired processing.

This method is effective when the amount of data to be processed is relatively small and high-speed processing is not required.

However, as society becomes more information-oriented, it has become necessary to perform operations on large amounts of data to detect patterns that span between one word and the next. - A circuit that performs parallel conversion is desired.

[Problem that the invention seeks to solve]

However, as described above, in the conventional method, input code examples are shifted one bit at a time, so there is a problem in that it takes time to extract data that spans word boundaries. In the past, when other processes such as encoding and decoding took time, the time it took to retrieve data that spanned word boundaries did not pose much of a problem. However, as the processing time for encoding and decoding becomes faster due to advances in circuit technology, and as the amount of encoding per line increases due to higher resolution operations, the processing speed for data retrieval increases. It becomes a problem.

[Contents of originality of the invention over the prior art] The present invention is unique in that it handles input parallel data as it is without first converting it into serial data, compared to the conventional method described above. have content.

[Means for solving problems]

The parallel-to-parallel conversion circuit of the present invention has m bits (
Two sets of m-bit wide input registers that alternately latch data input in parallel (m is a constant of 2 or more), and n-bit (m ≥ n) by shifting the input register value by arbitrary bits. It has a shift circuit that can compare the number of shifts, a shift number integrator that integrates the number of shifts, and a latch pulse generation circuit that generates a latch pulse for the input register based on the detected value of the shift number integrator.

[Example 1] Next, Example 1 of the present invention will be described with reference to the drawings.

FIG. 1.2.3 shows Example 1 of the present invention. A block diagram of a first embodiment of a parallel-to-parallel conversion circuit according to the present invention is shown in FIG. The parallel-to-parallel conversion circuit of the present invention includes input registers 101 and 102, and a multiplexer 40.
1,402, a barrel shifter 403, a latch pulse generator 106, and a shift number integrator 107.

In this example as well, it is assumed that the data for both input and output is 8 bits. Also, in the figure, the bit order of each register is MSB at the top and LSB at the bottom.

FIG. 2 is an example of an input bit string to be processed.

In the figure, data is handled in units of 8 bits.

Moreover, FIG. 3 is an example of the operation of the first embodiment of the present invention.

Next, the operation of the first embodiment of the present invention will be explained.

First, the first byte of the input bit string shown in FIG. 2 is latched into the input register 101, and the second byte is latched into the input register 102. The input data is then alternately input one byte at a time to the input register 101 and then to the input register 102, in this order.

Multiplexers 401 and 402 input data from input register 101 or input register 102. Initially, data is input from input register 101 to multiplexer 401 and from input register 102 to multiplexer 402. This input signal is provided by shift number integrator 107. The shift number integrator 107 inputs the shift number from the outside and provides the shift number to the barrel shifter 403, and simultaneously integrates the input shift number one after another. The barrel shifter 403 counts the given number of shifts from the MSB side, and outputs data of 8 bits starting from the (number of shifts + 1) bit. When the shift number integrator 107 adds up the number of shifts to 8, the shift number integrator 107 sends a signal to the latch pulse generator 106 . Latch pulse generator 1
06 outputs a latch signal to the input register 101 and latches the third byte of data into the input register 101.

The shift number integrator 107 is a multiplexer 401゜402
This time, data is input from the input register 102 to the multiplexer 401 and from the input register 101 to the multiplexer 402. That is, the second byte of the input bit string is input to the multiplexer 401, and the third byte of the input bit string is input to the multiplexer 402. Therefore, the LSB side of the barrel shifter 403 always contains the byte that was input first.

In this example, consider the case where 8 consecutive bits are extracted from the 8th bit counting from the beginning of input data. Starting from the state where the first byte is input to the input register 101, the second byte is input to the input register 102.
Even if it takes one clock to latch data into the clock and multiplexers 401 and 402 and select the data with the barrel shifter 403, it only takes two to four clocks in total. In reality, input to the input register can be performed simultaneously with the shift operation using the previous data, so it can be said that it actually takes one clock to take out the data.

[Embodiment 2] FIG. 4 shows an example 2 of the present invention, and FIG. 5 shows an operation example of the second embodiment of the present invention. Embodiment 2 of the present invention is an example in which the same functions as Embodiment 1 are realized using a barrel shifter.

The parallel-to-parallel conversion circuit in FIG. 4 includes input registers 101, 102 . Barrel shifter 103.104,
It is composed of an output register 105, a latch pulse generator 106, and a shift number integrator 107.

In this example, consider the case where 8 consecutive bits are extracted from the 8th bit counting from the beginning of input data. As in the first embodiment, the first byte of the input bit string is stored in the input register 10.
1 and the 2nd byte are latched into the input register 102, respectively. From now on, the input data is input to the input register 101,
One byte at a time is alternately input to the input register 102.

Next, the input register 101 is input to the barrel shifter 103, and the input register 102 is input to the barrel shifter 104. The shift number integrator 107 inputs the shift number from the outside and provides it to the barrel shifters 103 and 104. Now, if we take out 8 consecutive bits from the 8th bit counting from the beginning of the input data, the MSB of the barrel shifter 103 becomes the LSB of the output register 105, and the 7th bit from the LSB of the barrel shifter 104 becomes the 2 bits of the output register 105. The shift number integrator 107 shifts 7 bits to the LSB side for the barrel shifter 103, and shifts the MS to the MSB side for the barrel shifter 104 so that the shift number integrator 107 enters from the first to the eighth bit.
A 1-bit shift signal is applied to the B side.

In the output register 105, the barrel shifter 103,1.0
The logical OR of the data input from 4 is taken as output data. After this, when the shift number in the shift number integrator 107 reaches 8, the shift number integrator 1.07 sends a signal to the latch pulse generator 106, and the latch pulse generator 106 sends a latch signal to the input register 101. 3
Latch the byte of data into the input register 101,
This operation is similar to the operation in the first embodiment.

In this example as well, if the time required for inputting data to the input register is ignored, the number of clocks required for data extraction is only one clock.

〔Effect of the invention〕

As explained above, by applying the present invention,
It is possible to quickly extract n bits from arbitrary positions of data input in units of m blocks, especially data spanning word boundaries.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of a parallel-to-parallel conversion circuit according to the present invention, FIG. 2 is an example of an input bit string to be processed, FIG. 3 is an example of the operation of the first embodiment of the present invention, and FIG. Embodiment 2 of the present invention, FIG. 5 is an example of operation of Embodiment 2 of the present invention,
FIG. 6 is a block diagram of a conventional example, and FIG. 7 shows an example of the operation of this conventional example. 101... Input register, 102...
Input register, 103... Barrel shifter, 10
4... Barrel shifter, 105... Output register, 106... Latch pulse generator, 1
07...Shift number integrator, 401...
Multiplexer, 402...Multiplexer,
403... Barrel shifter, 601...
Shift register, 602...output register,
603... Latch pulse generator, 604...
...Shift number integration circuit. Agent Patent Attorney Shinta Otsuzu Uchihara

Claims (1)

[Claims] Two sets of bit-width input registers alternately latch data input in parallel in units of m bits (m is a constant greater than or equal to 2), and the input register values can be shifted by arbitrary bits to register n bits (m≧n). ), a shift number integrator that adds up the number of shifts, and a latch pulse generation circuit that generates a latch pulse for the input register based on the integrated value of the shift number integrator. 1. A parallel-to-parallel conversion circuit which extracts fixed length n bits from arbitrary positions in a continuous bit string in one clock.