JPS61157935A - Arithmetic logic unit - Google Patents

Abstract

PURPOSE:To obtain an arithmetic logic unit for generating an arithmetic state signal corresponding to the effective bit length of I/O data to be calculated by providing a circuit for selecting the arithmetic state signal generated at every bit. CONSTITUTION:Two types of input data 101 and 102 are inputted to an arithmetic circuit 103 at every corresponding bit. On the basis of these input data and a carry signal 106 corresponding to a low order bit from an arithmetic circuit 103, it executes the arithmetic in accordance with an arithmetic mode control signal 105 generated by an arithmetic mode control circuit 104. The carry signal 106 to the arithmetic circuit 103 corresponding to the output data 107 of the arithmetic result and a high order bit is generated. The carry signal 106 generated by each arithmetic circuit 103 is further inputted to a carry signal selecting circuit 110, while the arithmetic result output data 107 is further inputted to a code selecting circuit 111, a zero signal detecting circuit 108 and a zero signal selecting circuit 112.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic and logic operation unit in a data processing system in which data having various effective bit lengths coexist.

Conventional technology An example of a conventional arithmetic and logic operation device (filage, M.

Morr is Mano, co-translated by Shunji Okuyo and Noriyuki Inoue, Computer Logical Design J, March 1, 1953, Kyoritsu Shuppan, p. 97) is shown in Figure 2.

FIG. 2 is an example of an arithmetic and logic operation device that performs operations on two input data having a length of 4 bits. 2C・1 and 202 are input data to be operated on, 203 is an arithmetic circuit that performs an operation between corresponding bits of each of the above input data, and 204 is an operation mode in the arithmetic circuit 203 (for example, AND operation, addition, etc.). ) control signal 205
206 is a signal generated by each arithmetic circuit 203, and 207 is an arithmetic result output of each arithmetic circuit 203. The operation will be explained using an example in which addition is performed between two input data 201 and 202. Input data 201 is A1 (i == O ~ 3, but 1 = 0 is MS
Let it be B. ), the input data 202 is B1, and a carry signal Ci+1 . Assuming that the calculation result output is Fi and the generated carry signal is C, the calculation circuit 203 performs the calculation shown by the following equation.

F, = (A, ■Bi) Ci+1 C, = A, B, + (A, ■Bi) CI+1 However, C
4=o, and ■ represents an exclusive OR operation.

Apart from the operation result output 207 as described above, an arithmetic and logic operation unit generally generates an operation status signal according to the operation result. In FIG. 2, 208 indicates a carry signal from the most significant position, 209 indicates an overflow signal, 210 indicates a decimal sign signal, and 211 indicates a zero signal. These operation status signals are used directly or once stored in a register for use in determining program conditions.

Problems to be Solved by the Invention However, in the above configuration, the calculation state signal 2
08 to 211 have meaning only when the calculation target is data of a fixed length with an effective bit length (in the example of FIG. 2, both input data and output data are 4 bits). In a data processing system where data with various effective bit lengths coexist, overflow, zero signals, etc. may occur with respect to the effective bit length of the data that is the actual operation target (especially the effective bit length of the register that stores the operation result output). becomes important. For example, in the example of FIG. 2, 4-bit data 0111 and 3-bit data 001
When adding , and storing the result in a register with an effective bit length of 3 pits, the operation result is 1oOo, and the arithmetic and logic unit in Figure 2 generates neither a zero signal nor a carry signal (or the signal is logic However, looking at the register that stores the result, the stored data is 00003 bits, and both the zero signal and the carry signal should generate logic 11#.

As described above, the arithmetic and logic operation device having the configuration shown in FIG. 2 has a problem in that no significant operation status signal is generated for data having various effective bit lengths.

In view of this, it is an object of the present invention to provide an arithmetic and logic operation device that selectively generates an operation state signal according to the effective bit length and operation mode of operation target input data and operation result output data.

Means for Solving the Problems In order to solve the above problems, the present invention provides an arithmetic circuit that generates an arithmetic state signal according to the arithmetic result for each bit, and an arithmetic circuit that generates an arithmetic state signal that is generated for each bit. A selection circuit that selects and outputs one of the inputs, and a selection signal generation circuit that generates a control signal to the selection circuit using the effective bit length of the input data to be operated on and the effective bit length of the operation result output data as input data. It is an arithmetic and logic operation unit equipped with.

Operation According to the above-described configuration, the present invention selectively generates a significant operation status signal as an operation status signal for the entire arithmetic and logic unit, depending on the effective bit length of the data to be operated on and the operation mode.

Embodiment FIG. 1 is a block diagram showing an embodiment of the arithmetic and logic operation device of the present invention. FIG. 1 shows an example in which an operation is performed on two input data having a maximum effective bit length of 4 bits. 101 and 102 are input data to be calculated,
103 is an arithmetic circuit that performs an operation between the corresponding bits of each of the above input data; 104 is a circuit that generates a signal 106 that controls the mode of operation in the arithmetic circuit 103;
106 is a carry signal generated by each arithmetic circuit 103;
107 is the calculation result output of each calculation circuit 103.

10B is a zero detection circuit, 109 is an overflow detection circuit, 1
10 is a selection circuit that selects two adjacent bits from the carry signal generated by each arithmetic circuit 103; 111 is a selection circuit that selects one bit from the operation result output generated by each arithmetic circuit 103; 112 is a selection circuit for each of the arithmetic circuits 103; Zero detection circuit 108
117 is a selection control signal 1 for the selection circuits 110 to 112 described above.
A circuit that generates 18, 119 input data 101, 10
2 and data regarding the effective bit length of the output data 107, 113 is a carry signal corresponding to the upper bit of the two carry signals selected by the carry signal selection circuit 110, and 114 is selected by the carry signal selection circuit. 116 is a code signal selected by the code signal selection circuit 111, and 116 is a zero signal selected by the zero signal selection circuit 112. .

The operation of the arithmetic and logic operation device of this embodiment configured as described above will be explained below.

Input data 101 and 102 are input to an arithmetic circuit 103 for each corresponding bit. In each arithmetic circuit 103, the arithmetic circuit 1 corresponding to these input data and lower bits is
Based on the carry signal 106 of 03, an operation is performed according to the operation mode control signal 1051C generated by the operation mode control circuit 104, and a carry is carried to the operation circuit 103 corresponding to the operation result output data 107 and the upper bit. signal 10
Generate 6. The carry signal 106 generated by each arithmetic circuit 103 is further input to a carry signal selection circuit 110,
The operation result output data 107 is further input to a code selection circuit 111, a zero signal detection circuit 108, and a zero signal selection circuit 112.

In the example of FIG. 1, the input data 101 is Ai (i=0~
3) If the input data 102 is B t (1=O~3), the carry signal 106 to the corresponding arithmetic circuit 103 is C, and the arithmetic result output data 1+j 107 is Fi, then the carry Ck (k=o-3) is input to the signal selection circuit 110, and 5k=F, (k=o-3) and the cello signal are input to the code signal selection circuit 111. For example, input data 101 has an effective pit length of 4 bits, data A=CN11. Consider the case where the input data 102 is data B=(0)001 with an effective bit length of 3 bits and the operation mode is addition.

(However, if the input data is less than the maximum effective bit length of the arithmetic logic unit, it is assumed that 0 is filled from the upper part.) Each arithmetic circuit 103 performs the operation shown by the following equation.

Fi=(A,■Bi)C141 c,=A,B,+(A,■Bi)C1+1However, C4=
0, and ■ represents exclusive OR.

As a result of this operation, F = 1, F = Q, F2 = Q, F3 = QC = O
C=1G=1 and C3=1 0 1 1 T 2 are generated.゛Therefore, in the carry signal selection circuit 110, C=o, C=1
．． C2=1. C3=1, but the code signal selection circuit 111 has S=1 S=o, 52=o, S3=.

Let us consider a case where the operation result output data 107, in which Ov 1 and Ov 1 are respectively input to the zero signal selection circuit 112, is stored in a register with an effective bit length of 3 bits.

Input/output data valid bit length data 119 (4 bits, 3 pifts, 3 bits in this example) is input to the selection signal generating circuit 117. For example, the effective bit length for generating the operation status signals 113 to 116 for the entire arithmetic and logic operation device is the effective pit length of the output data 107 (in this example, 3
(bit), carry signal selection circuit 1
10, C1("C4-3) and"2(=C4-(3
-1)), but in the code signal selection circuit 111, S, (=84
-3) In the force ζ zero signal selection circuit 112, Zl(''=4
A selection control signal 118 is generated in the selection signal generation circuit 117 so that -3) is selected.

As a result, the present arithmetic and logic unit uses C1=1 as the carry signal 113 and C4■C2= as the overflow signal 114.
0 as code signal 115 51=0 as zero signal 11
6 and outputs Z,=1.

In this embodiment, the arithmetic logic unit outputs four types of operation status signals, 113 to 116, but the present invention can be applied to other operation status signals.

In addition, the selection control signal 11 in the selection signal generation circuit 117
The generation logic of No. 8 is not limited to the above example either.

Effects of the Invention As described above, according to the present invention, by providing a circuit that selects the calculation status signal generated for each bit, It is possible to configure an arithmetic logic unit that generates arithmetic status signals, and this has a great practical effect in a data processing system in which data with various effective pit lengths coexist.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic and logic operation device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional arithmetic and logic operation device. 103... Arithmetic circuit, 104... Arithmetic mode control circuit, 110, 111, 112...
Arithmetic state signal selection circuit, 113-116...Arithmetic state signal, 117...Selection signal generation circuit.

Claims (1)

[Claims] an arithmetic circuit that performs an arithmetic operation on each corresponding bit of a plurality of arithmetic target input data and generates an arithmetic state signal according to the arithmetic result for each bit; an arithmetic mode control circuit that specifies an arithmetic mode of the arithmetic circuit; , a selection circuit that receives the operation status signals generated for each bit as input and selects and outputs one of them, and the effective bit length of the operation target input data and the effective bit length of the operation result output data as input data. , comprising a selection signal generation circuit that generates a selection control signal to the selection circuit, and generates an operation status signal for the entire arithmetic device according to the effective bit length of the operation target input data and the operation result output data. an arithmetic and logic unit.