JPS63298436A - Arithmetic logical operation unit - Google Patents

Abstract

PURPOSE:To process plural data to one time as a single operation subject input data and shortening the processing time by stopping the transmission of the carry signals produced for each bit at an optional bit position and supplying an input carry signal to an optional bit position via a selection circuit. CONSTITUTION:An arithmetic circuit 103 is used together with a carry signal selecting circuit 109 and a selection signal generating circuit 111. The circuit 109 stops the transmission of the carry signals produced by the circuit 103 at an optional bit position to the circuit 103 corresponding to the higher level bits. Then an operation subject input carry signal is supplied to the circuit 103 corresponding to an optional bit. Thus it is possible to process plural data packed into a single word at one time as a single operation subject input data in accordance with each valid bit length and bit position.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic and logic operation unit in a data processing system in which there is data in which a plurality of data having various effective bit lengths are packed in one word. .

゛Conventional Technology An example of a conventional arithmetic and logic operation device (for example, "Logic Design of Computers" by Morris Nano, co-translated by Shunji Okuyo and Noriyuki Inoue, March 1, 1983, Kyoritsu Shuppan, P. 97) is shown in FIG.

FIG. 2 is an example of an arithmetic and logic operation device that performs operations on two input data having a length of 4 bits. 201 and 202 are input data to be operated on, 203 is an arithmetic circuit that performs an operation between corresponding bits of each input data, and 204 is an operation mode in the arithmetic circuit 203 (
206 is an input carry signal to be operated on to the arithmetic circuit 203 corresponding to the least significant bit; 207 is generated by each arithmetic circuit 203 A carry signal 208 is the operation result output data of each arithmetic circuit 203, and 209 is an output carry signal from the arithmetic circuit 203 corresponding to the most significant bit.

The operation will be explained by taking as an example the case where addition is performed between two input data 201 and 202. Ai the input data 201
(i=o~3. However, i=o1MsB.), input data 202 is Bi (l=o~3), carry signal to the arithmetic circuit 203 corresponding to the first bit is C3, arithmetic result output Assuming that the data is 1+1 F8 and the generated carry signal is Cth, the arithmetic circuit 203 performs the calculation shown in the following equation.

Fi= (Ai■Bi)Ci+1 C= A B + (A, ■Bi)Ci+11 t
l However, the input carry signal C4 is set to 1, and ■ represents an exclusive OR operation.

Problems to be Solved by the Invention However, in the above configuration, when data in which a plurality of pieces of data having various effective bit lengths are packed in one word is to be operated on, the operation result output data 2
08 and output carry signal 209 have no meaning.

In a data processing system in which the above-mentioned data exists, operation result output data and output carry signals are required for each piece of packed data that is the subject of actual operation. For example, in the example shown in Figure 2, the 2-bit data 0
When adding 4-bit data 0111 packed with 1 and 2-bit data 11 and 4-bit data o011 packed with 2-bit data 00 and 2-bit data 11, the calculation result becomes 1010, and the output is A logic "0" is generated as a carry signal. However, if we focus on each piece of packed data that is the object of the operation, the operation result will be OL, which is packed with OL by the upper 2 bits and 10 by the lower 2 bits, and the output carry signal will also be a logic "0" by the upper 2 bits and a logic "0" by the lower 2 bits. Logic with 2 bits @1″
should be generated. Therefore, in an arithmetic and logic operation unit having the configuration shown in Fig. 2, when data in which multiple pieces of data with various effective bit lengths are packed into one word is to be operated on, each packed data Either it is necessary to have a dedicated arithmetic and logic operation unit for each data, or it is necessary to process each piece of data by the number of packed data, and in the former case, the amount of hardware is However, in the latter case, there is a disadvantage that the processing time increases.

As mentioned above, in an arithmetic logic unit having the configuration shown in Figure 2, significant operation result output data and The problem was that a carry signal was not generated.

In view of this, the present invention provides an arithmetic and logic operation device that processes a plurality of data packed into one word at once as one operation target input data according to each effective bit length and bit position. With the goal.

Means for Solving the Problems In order to solve the above problems, the present invention provides an arithmetic circuit that generates a carry signal according to the arithmetic result for each bit, and a carry signal generated by the arithmetic circuit for each bit. a carry signal selection circuit that stops propagation of the carry signal to the arithmetic circuit corresponding to the upper bit at an arbitrary bit position and inputs the input carry signal to be operated on to the arithmetic circuit corresponding to the arbitrary bit; The present invention is an arithmetic and logic operation device that includes a selection signal generation circuit that generates a selection control signal to a carry signal selection circuit.

Effect of the present invention With the above-described configuration, the carry signal selection circuit
The propagation of the carry signal generated by the arithmetic circuit for each bit to the arithmetic circuit corresponding to the upper bit is stopped at an arbitrary bit position, and the input carry signal to be operated is input to the arithmetic circuit corresponding to the arbitrary bit. Therefore, a plurality of pieces of data packed into one word are processed at once as one operation target input data according to each effective bit length and bit position.

Embodiment FIG. 1 is a block diagram showing an embodiment of the arithmetic and logic operation device of the present invention. FIG. 1 shows an example in which an operation is performed on two input data having a maximum effective bit length of 4 bits. 101 and 102 are input data to be calculated,
103 is i between corresponding bits of each of the above input data
104 is a circuit that generates a signal 105 that controls the mode of calculation in the calculation circuit 103, 106 is an input carry signal to be calculated, and 107 is an output carry generated by each calculation circuit 103. signal, 108
is the calculation result output data of each calculation circuit 103, 109
111 is a selection circuit that selects one signal from the input carry signal 106 and each carry signal 107; 111 is a circuit that generates a selection control signal 112 for each carry signal selection circuit 109; and 110 is a selection circuit for each carry signal. Signal selection circuit 109
This is the carry signal selected by .

The operation of the arithmetic and logic operation device of this embodiment configured as described above will be explained below.

Input data 101 and 102 are input to an arithmetic circuit 103 for each corresponding bit. In each wave circuit 1o3, based on these input data and the carry signal 110 from the carry signal selection circuit 109 corresponding to the same bit (however, in the case of the arithmetic circuit 103 corresponding to the least significant bit, the carry (The input carry signal 106 is used instead of the signal 110.) An operation is performed according to the operation mode control signal 106, and the operation result output data 108 and the carry signal selection circuit 109 corresponding to the upper bit are sent. An output carry signal 107 is generated as input and output to the outside.

In addition, each carry signal selection circuit 109 selects one of the output carry signal 107 and input carry signal 106 from the arithmetic circuit 103 corresponding to the lower bit according to the carry signal selection control signal 112. It is selected as the carry signal 11o that is input to the arithmetic circuit 103 corresponding to the same bit.

In the example of FIG. 1, the input data 101 is Ai (i=o~
3), input data 1o2 is set to B, (i=o~3), and carry signal 11 is sent to the tear calculation circuit 103 corresponding to the i-th bit.
0 is Di1 calculation result output 1 data 108 is Fi, output carry signal 107 is Ci, input carry signal 106 is D
Set it to 4. For example, input data 101 has an effective bit length of 2
Bit data o1 and effective bit length 2 bit data 1
Data A of 4 bits packed with 1 = 0111, human data 102 is data o with an effective pit length of 2 pits.

and data 11 with an effective bit length of 2 bits are packed 4
Consider the case where bit data B=0011, input carry signal 106 is D4=0, and the calculation mode is addition.

At this time, Do=C in each carry signal selection circuit
A carry signal selection control signal 112 is generated in the selection signal generation circuit 111 so that 1.D1=D4.D2=C3 is selected.

Further, each arithmetic circuit 103 performs an arithmetic operation expressed by the following equation.

F, = (A, (EIB,)D.

C,=At　Bi+　(A,■Bl)D.

However, ■ represents exclusive OR.

As a result of this operation, Fo=o, E1=1. F2=1. F3=OC=o, C=
1. C2=1. C3=1 is generated.

As a result, this arithmetic and logic operation device outputs F as the operation result output data of the upper 2 bits. F1=01. C0=1 is output as a carry signal, and C2=1 is output as a 12132109 carry signal as the operation result output data of the lower two bits.

Effects of the Invention As described above, according to the present invention, a selection circuit is provided which stops the propagation of a carry signal generated for each bit at an arbitrary bit position and inputs an input carry signal to an arbitrary pit position. By doing this, it is possible to configure an arithmetic and logic operation device that processes multiple pieces of data packed in one word at once as one operation target input data according to each effective bit length and pit position. This has great practical effects in a data processing system where there is data in which a plurality of pieces of data having an effective bit length are packed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an arithmetic and logic operation device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a row of conventional arithmetic and logic operation devices. 103... Arithmetic circuit, 104... Arithmetic mode control circuit, 109... Carry signal selection circuit, 106° 107.110... Carry signal,
111...Selection signal generation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure

Claims (1)

[Claims] an arithmetic circuit that performs an arithmetic operation on each corresponding bit of a plurality of arithmetic target input data and generates a carry signal according to the arithmetic result for each bit; an arithmetic mode control circuit that specifies an arithmetic mode of the arithmetic circuit; , the arithmetic circuit stops propagation of the carry signal generated by the arithmetic circuit for each bit to the arithmetic circuit corresponding to the upper bit at an arbitrary bit position, and transfers the input carry signal to be operated on to the arithmetic circuit corresponding to the arbitrary bit. and a selection signal generation circuit that generates a selection control signal to the carry signal selection circuit. An arithmetic and logic operation device that processes input data as one operation target at one time according to its position.