JPS63163654A - Device for selecting input/output unit - Google Patents

Abstract

PURPOSE:To eliminate the need of setting by a dip switch, etc., by providing an arithmetic means by which value is changed at every passing of an address signal through plural input/output units in order, and performing the transfer of an input/output signal between the input/output unit in which an arithmetic result value reaches a prescribed value. CONSTITUTION:For example, when (i)=3, that is, a third input/output unit is selected, since it is expressed as (i)=0011 in a binary number, the complement of 2 of the (i) goes to 1101, and a sequencer main body 1 outputs 1101 as an address signal A. The address signal goes to 1110 by adding 1 when it passes through a first input/output unit, and goes to 1111 at a second input/output unit, therefore, at a third input/output unit, it goes to 10,000(=2<4>), then, a carry signal (H) is generated at an adder 4. The carry signal becomes a signal which operates an input/output control circuit 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to sequencers and microprocessors (CPUs).
The present invention relates to a device for selecting an input/output unit to be connected as an input/output unit of a signal processing device or a control device such as the above.

[Prior Art] For example, in a sequencer in which the number of contacts for inputting and outputting signals can be changed as necessary, an additional input/output device, generally called an input/output unit, is connected to the main body of the sequencer, and the number of contacts increases. If there are many input/output units, multiple input/output units are used. In this case, the sequencer body is
Multiple input/output units to be connected for input/output must be distinguished in some way. For example, if three input/output units each having 8 contacts are installed, the contact of the first unit input/output by setting a number (address) for each contact, such as number 1 to 8 for the second unit, number 9 to 16 for the contact of the third unit, number 17 to 24 for the third unit, etc. An address setting method is used to identify the unit, and these address settings are performed using dips (DIPs) provided on each input/output unit.
P) This was done using a digital switch such as a switch.

[Problems to be Solved by the Invention] However, in the above address setting method, the user has to set the dip switches according to the number of input/output units to be connected, and the setting is complicated.
Another problem is that incorrect settings may occur.

[Means for solving the problems] The present invention has been made in view of the above problems, and
It is an object of the present invention to provide an input/output unit selection device that can arbitrarily select a plurality of input/output units attached to a device such as a sequencer without making settings using digital switches as described above.

Therefore, the present invention provides an address bus that transmits an address signal indicating a designated input/output unit from among a plurality of input/output units, and a value of the address signal that is transmitted each time the address signal sequentially passes through the plurality of input/output units. The input/output signal is transmitted to and received from the input/output unit when the calculation result of the calculation means reaches a predetermined value.

[Example] FIG. 1 shows the overall configuration of an embodiment of the present invention.

In the figure, 1 is a sequencer main body, and this sequencer main body 1 has six address buses AO to A5, eight wooden data buses Do to D7, and a control signal line 3 as an output section for attaching an input/output unit 2. Of the six address buses, AO to A3 are used to select (designate) which input/output unit 2 is to be used for input/output. In other words, address buses Ao to A3 are A 4-bit address signal A indicating the input/output unit 2 designated for input/output is transmitted to the input/output unit 2.

Therefore, up to 24=le input/output units can be connected to the sequencer main body l.

The remaining two address buses A4 and A5 are for transmitting signal B indicating which 8 bits to use when the input/output of the input/output unit 2 selected as described above is 16 bits or 32 bits. be.

The control signal line 3 transmits the 'MVJ4 signal as an input and output trigger output from the sequencer main body 1, and the data bus Do-D7 transmits data signals input and output to the connected input/output unit 2. Transmit.

The input/output unit 2 described above has a bus input section connected to the bus output section of the sequencer main body 1, and also has a bus output section similar to the sequencer main body 1. Therefore, the first input/output unit is connected to the bus output section of the sequencer main body l via its bus input section, but the second and subsequent input/output units are sequentially connected to the bus output section of the previous input/output unit 2. ,
Numbers 1, 2, +-++, and n are assigned in that order.

FIG. 2 shows an example of the circuit configuration of a unit/total selection device provided corresponding to the input/output unit 2 connected to the sequencer body 1.

First, an adder 4 is connected to the four address buses AO-A3 as an arithmetic means for changing the value of the address signal A. This adder 4 is configured to add 1 to the value of address signal A for each input/output unit and output the result, and to output a carry signal when the addition result reaches a predetermined value. Ru.

Specifically, adder 4 adds 1 (addition signals B3 to Bo) to the inputs (signals from address buses A3 to AO) and outputs the next value of the address signal (Σ3 to Σ0). Therefore, when the address signal A sequentially passes through a plurality of input/output units 2, it increases by 1 each time, and
Each adder 4 outputs a value indicating . Further, when the addition result (Σ3 to Σ0) reaches a predetermined value (24=113), the adder 4 outputs H" (carry signal) to the CY boat. This carry signal is sent to the inverter 5.
The inverted carry signal is inverted to ``L'' and becomes one of the inputs to the input control circuit 8a described later.The inverted carry signal is inputted together with the control signal to the AND circuit 6, and the AND output is input to the output control circuit 8a described later. This is one of the inputs to 8b.

On the other hand, Hatecoder 7 is connected to two address buses A4 and A5.
is connected, and its output is sent to the input/output control circuit 8. The input/output control circuit 8 has four circuits each consisting of an AND element.
Four input control circuits 8a and four output control circuits 8b
The inverted carry signal and the signal from the decoder 7 are input to each input control circuit 8a.
Signals from the AND circuit 6 and the decoder 7 are input to each output control circuit 8b.

The input/output circuit 9 of each input/output unit 2 is connected to the output side of the input/output control circuit 8. This input/output circuit 9 is
It includes a gate that is interposed between the data bus n6-07 and an external circuit (not shown) and is opened and closed by a signal from the input/output control circuit 8. It inputs and outputs 8-bit data signals.

Specifically, the input/output circuit 9 includes four input circuits 9a (numbers θ to 3) connected to the input control circuit 8a and an output control circuit 8.
The input circuit 9a is divided into four output circuits 9b (numbered O to 3) connected to the external circuit, and is connected to an external circuit to transmit and receive input/output signals.
Each of the output circuits 9b is composed of a latch circuit, but they can also be composed of a transistor circuit, a triac circuit, or a relay circuit.

Therefore, the carry signal from inverter 5 and decoder 5
When both output signals from the input control circuit 8a are "L", the input control circuit 8a
The output becomes "H" and is given to the input circuit 9a as a gate signal. Further, when the output signals from the AND circuit 6 and the decoder 7 are both "L", the output of the output control circuit 8b becomes "H" and is given to the output circuit 9b as a gate signal.

Next, the operation of the embodiment will be explained.

FIG. 3 is a block diagram showing the case where the i-th input/output unit is selected.

First, the sequencer main body 1 sends the two's complement of i, ie (-1), to the address bus A as an address signal for selecting the i-th input/output unit.

~Output to A3. This address signal A is incremented by "l" every time it passes through each outgoing crab unit, so (i-
1) When passing through the th input/output unit, (-i)+
(i-1)=-1 When this -1 is input to the i-th input/output unit, 1 is added by the corresponding adder 4, and the result becomes O. At the same time, the carry signal of the adder 4 becomes H''. This operation is performed using binary numbers as follows.

For example, when i=3, that is, when selecting the third input/output unit, it is expressed as 1=0011 in binary, so
The two's complement number of i is 1101, and the sequencer body l outputs this as the address signal A. When this address signal passes through the first input/output unit, it is incremented by 1 and becomes 1110, and in the second input/output unit it becomes 111.
1, therefore 10000 for 3rd entry/output Kanini/to
(=24), causing the adder 4 to generate a carry signal "H". As described above, this carry signal becomes a signal for operating the input/output control circuit 8.

On the other hand, the signals on the address buses A4 and A5 are input to the decoder included in the input/output control circuit 8, and as described above, the input/output control circuit 8 specifies one of the input/output circuits 9 with numbers θ to 3. A gate signal is output. When the sequencer main body 1 reads data from an external circuit, the decoder output from the input/output control circuit 8 and the carry signal from the adder 4 become the gate inputs of the input circuit 9a; In addition to the signal in the case of , the control signal from the sequencer main body 1 becomes the gate input of the output circuit 9b. Therefore, the control signal in this embodiment is a write signal.

Although the illustrated embodiment has been described above, the present invention is not limited thereto.

For example, the number of address buses and data buses is not limited to the above number, but can be increased as appropriate depending on the number of input/output units to be added or the CPU in the sequencer.

Furthermore, the arithmetic means for the address signals transmitted by the address bus is not limited to an adder that adds 2, but may be any arithmetic unit as long as each input/output unit can be specified.

[Effects of the Invention] As described above, the present invention provides an address bus that transmits an address signal indicating a designated input/output unit from among a plurality of input/output units, and an address bus that transmits an address signal indicating a designated input/output unit from among a plurality of input/output units. It is equipped with arithmetic means that changes the value each time it passes sequentially, and when the arithmetic result reaches a predetermined value, input/output signals are sent and received to and from the input/output unit, so dip switches etc. This eliminates the need for settings using other devices, eliminating the complexity and risk of incorrect settings associated with conventional methods. Furthermore, it is possible to attach as many input/output units as possible within the capabilities of the sequencer main body, and to easily select any unit. Furthermore, even if the number of input/output points per unit is different, the corresponding input/output unit can be automatically selected, and the number of input/output units can be freely increased by increasing the number of address buses. .

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the overall configuration of an embodiment of the present invention, Fig. 2 is a diagram showing an example of the configuration of a circuit for selecting an input/output unit, and Fig. 3 is a diagram showing an example of the configuration of a circuit for selecting an input/output unit. It is an explanatory diagram when selecting a unit. 1-111 sequencer main body, 2-111 output unit, 3-111 control signal line, 4-111 adder, 5-111 inverter, 6----A N D circuit , 7--decoder, 8-1-1 output control circuit, 9-1-1 output circuit, A, -A5--address bus, no -D7--data bus. Patent Applicant Yamatake Honeywell Co., Ltd. Agent Patent Attorney Shindo Hori Patent Attorney Kazuko Hori Figure 2 Figure 3 Procedure Nei City Authorization (Spontaneous) February 4, 1986

Claims (2)

[Claims] (1) An address bus that transmits an address signal indicating a designated input/output unit from among a plurality of input/output units, and whose value changes each time the address signal passes through the plurality of input/output units in sequence. 1. An input/output unit selection device comprising: arithmetic means, and transmits/receives an input/output signal to/from the input/output unit when a calculation result of the arithmetic means reaches a predetermined value. (2) The calculation means comprises an adder that adds 1 to the value of the address signal for each input/output unit and outputs a carry signal when the addition result reaches a predetermined value. The input/output unit selection device according to item 1.