JPS61255433A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To execute the calculation of the data of 32 bits and the calculation of the data of 16 bits easily and at a high speed in the same manner by providing two sets of ALU parts for the data of 16 bits. CONSTITUTION:Two sets (4a and 4b) of ALU parts of the data of 16 bits are provided, a selector 8 is placed so that the carrying signal from the highest order bit of the second ALU part 4b or the carrying signal from the external part can be connected to a carrying bit input terminal 9a of the first ALU part 4a, and by the selector 8, the carrying signal from the ALU part 4b is connected so that it can be inputted to a carrying bit input terminal 9a of the ALU part 4a, the unit is operated as the arithmetic unit of the data of 32 bits, and when a carrying signal CR from the external part is connected so that it can be inputted to a carrying bit input terminal 9a of the ALU part 4a, the unit is operated as two sets of the arithmetic units of the data of 16 bits. When the unit is used as 16 bits, swapping circuits 7a, 7b and 7c are provided so that the data can be calculated by any ALU part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device capable of executing operations on 32-bit data and operations on 16-bit data.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional device of this type, which is an Advanced Mioro-Device.
r Bipola published in 1983 by es inc.
r MicroprocessorLogic and
This is quoted from Section 5-5 of Interface J. In the figure, (la) and (lb) are the first and second internal registers, respectively, and (2a) and (2b) are the first and second internal registers, respectively. The second latch portions (3a) and (3b) are respectively connected to the first latch portions (3a) and (3b). a second data source selection section; (4) is an arithmetic circuit (hereinafter abbreviated as ALU) section; (5a) and (5b) are respectively the first data source selection section; The second external input data line (6) is the calculation result output data line, which is the data line (5a).

(5b), +6) are all designed for 32-bit data.

The terminal of the ALU unit (4) to which 32 bits of data are input from the data source selection unit (3a) will be temporarily referred to as the first signal input terminal, and 32 bits of data will be input from the data source selection unit (3b). The terminal of the ALU section (4) will be temporarily referred to as a second signal input terminal.

Since the operation of the apparatus shown in FIG. 2 when performing arithmetic operations on 5-bit data is well known, a general explanation thereof will be omitted. The calculation result is output to the data line (6), and its contents are stored in the internal register sections (1&) and (lb), and are sent to the data source selection section (3a) via the latch sections (2a) and (2b). ) and (3b), so please select the data source selection section (3m) and (3b)! The input to the first and second signal input terminals of the J ALU unit (4) can be data of the results of previous calculations, depending on the necessity of calculation.

[Problem that the invention seeks to solve]

When performing ° operation on 16-bit data using the device shown in Fig. 2, the 16 bits are transmitted as the upper 16 bits of the data lines (5a) and (5b), or the latch section (2a)
.

(2b), and if you try to output it as the upper 16 bits of the data line (6), 9, due to the carry signal input from the outside of the ALU section (4), etc. The operation is performed by swapping the bits to the lower 16 bits, and the 16 bits of this operation result must be swapped back to the upper side and output on the data line (6). This swap is performed under program control. There was a problem that the processing speed slowed down when this was done.

This invention was made to solve the above-mentioned problems, and aims to provide an arithmetic device that can easily and quickly perform operations on 16-bit data as well as operations on 32-bit data. The purpose is

[Means for solving problems]

In this invention, two sets of ALU units for 16-bit data are provided, and the carry bit input terminal of the first ALU unit is connected to the second ALU unit.
A selector is provided to which a carry signal from the most significant bit of the LU section or a carry signal from an external source can be connected.
When the carry signal from the second χ section is connected to the carry bit input terminal of the first ALU section by this selector, it operates as an arithmetic unit for n-bit data, and the carry signal from the outside is input to the carry bit input terminal of the first ALU section. When connected to input to the carry bit input terminal of ALU section 1, two sets of 1
to operate as a 6-bit data arithmetic unit,
In addition, as an arithmetic unit for 16-bit data, a swap circuit is provided so that any ALU section can be used for any data.

[Effect]

According to this invention, by switching the selector, it can be used as an arithmetic device for n-bit data or as an arithmetic device for 16-bit data, and when operating as a 16-bit arithmetic device, swapping can be performed at high speed by the swap circuit. It can be carried out.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate corresponding data, and (lc
), (ld), (le), (If) are internal registers, (2c), (2d), (2e), (2f) are latch parts, (3c), (3d), (3e), (3f
) are data source sections, (4s and 4b) are ALU sections, respectively, and (7a) and (7b).

(7c) is a swap circuit, (8) is a selector,
(9a) and (9b) are carry bit input terminals, (10a) and (10b) are carry bit output terminals, and CR is a carry signal given from the outside.

(lc), (ld), (2c)-(2d), (
3c), (3d), and (4a) constitute the first OALU section, and (le), (lf)-(2e)-(2f), (3
e), (3f), and (4b) constitute the second ALU section, and the 11th and 2nd ALU sections have similar configurations, so hereinafter similar components will be referred to as the first ALU section. I will only explain about. (le), (ld), (2c), (2d).

(3c), (3d), and (41L) are (la) and (lb) in Figure 2, respectively.

The parts corresponding to (2a), (2b), (3a), (3b), and (41) correspond to 32-bit data in Fig. 1, whereas each part in Fig. 1 corresponds to 32-bit data. Each part is 16
The difference is that it corresponds to bit data.

When performing calculations on 32-bit data in the device shown in FIG. 1, the 9ALU section (4b
) carry bit output terminal (10b) and ALU section (4a
) is connected to the carry bit input terminal (9a) of the converter, and swapping is not performed in any of the swap circuits (7a), (7b), and (7c), the device in Fig. 1 is the same as the device in Fig. 2. It is clear that it works.

In the device shown in FIG. 1, by switching the selector (8),
Carry signal CR to carry bit input terminal (9m).

(9b), it becomes possible to perform operations on 16-bit data using either ALU section (4a) or (4b).

The ALU section (4a), (4b) selects the data source selection section (3).
c).

The terminal to which data from (3e) is input is called a first signal input terminal, and the terminal to which data from (3d) and (3f) are input is called a second signal input terminal. In the following explanation, for convenience of explanation, the data on the data line (5a) is input to the first signal input terminal, and the data on the latch parts (2d) and (2f) are input to the second signal input terminal. A data source selection unit (13c) for inputting data.

It is assumed that (13d), (13e), and (13f) are selected.

For example, when performing an operation on the upper 16 bits of the 32-bit data on the data line (5a), one method is to swap the data in the swap circuit (7a) and send the data to the ALU via the data source selection unit (311) t''. Part (4b)
The 16 bits of the operation result can be swapped by the swap circuit (7C) and output as the upper 16 bits of the n-bit data on the data line (6). , swap circuit (
It is also possible to output the lower 16 bits of data on the data line (6) without executing the swap in step 7c).

Alternatively, the upper 16 bits of data on the data line (5a) are sent to the ALU unit (4a) via the data source selection unit (3C) without being swapped in the swap circuit (7a).
input to the first signal input terminal of , and the 16 bits of the operation result are either not swapped in the swap circuit (7C) and used as the upper 16 bits of data on the data line (6), or swapped in the swap circuit (7C). Data line (6)
It can be output as upper 16 bits of data.

〔Effect of the invention〕

As described above, according to the present invention, two sets of ALU sections for 16-bit data are provided, and the carry bit input terminal of the first ALU section receives the carry signal from the carry bit output terminal of the second ALU section. , or a carry signal input from an external source.
This has the advantage that operations on 32-bit data and operations on 16-bit data can be executed equally easily and at high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. (3c), (3d), (3e), and (3f) are each a data source selection section, (4a) is a first ALU section,
(4b) is the second ALU section, (5a) and (5b) are the external input data lines, (6) is the output data line, (7a) is the I-th swap circuit, and (7b) is the second
swap circuit, (7c) is the third swap circuit, (8
) is a selector, (9m) and (9b) are carry bit input terminals, and (10a). (10b) is a carry bit output terminal, and CR is a carry pict for external input. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A first signal input terminal that inputs a 16-bit first signal, a second signal input terminal that inputs a 16-bit second signal, and a carry signal to the least significant bit of the 16 bits. A carry bit input terminal for inputting , a carry bit output terminal for outputting a carry signal from the most significant bit of the 16 bits, and inputting an external signal to the first signal input terminal,
a first data source selection unit that switches data to input a signal from a register that stores calculation results;
a second data source selection section that switches between inputting an external signal to the signal input terminal of the input terminal and inputting a signal from a register that stores the calculation result; and a signal output terminal that outputs the data of the calculation result. a first arithmetic circuit section having the same configuration as the first arithmetic circuit section; a carry signal output from the second arithmetic circuit section, or the first arithmetic operation from the outside; a selector that selects a carry signal to be input to the least significant bit of the circuit section and inputs the selected carry signal to the carry bit input terminal of the first arithmetic circuit section; The 32 bits of signals applied from the outside are inputted to the data source selection section of the first data source of the first and second arithmetic circuit sections as they are, or by swapping their upper 16 bits and lower 16 bits. A first swap circuit connected to the selection section, which inputs the 32-bit signal from the outside to the second data source selection section of the first and second arithmetic circuit sections as is or with its upper 16 bits. bottom 16
a second swap circuit that swaps the bits with the bits and connects to the second data source selection section of the first and second arithmetic circuit sections; a signal from the signal output terminal of the first and second arithmetic circuit sections; is input, the signal from the signal output terminal of the first arithmetic circuit section is the upper 16 bit signal of the n-bit signal output,
The signal from the signal output terminal of the second arithmetic circuit section is output as a lower 16-bit signal of the 32-bit signal output, or a third signal is output by swapping the signal inputs from the two signal output terminals. When equipped with a swap circuit and used as an arithmetic device for a 32-bit signal, the selector is connected to provide a carry signal output from the second arithmetic circuit section to a carry bit input terminal of the first arithmetic circuit section, When each of the swap circuits does not perform swapping and is used as a 16-bit signal arithmetic device, the selector connects the carry signal applied from the outside to the carry bit input terminal of the first arithmetic circuit section, and An arithmetic device characterized in that each swap circuit performs necessary swaps.