JPH03276229A - Microprocessor - Google Patents

Abstract

PURPOSE:To carry out both increment and decrement instructions at one time and in a single step by providing a register which increases and decreases the data at one time among those registers. CONSTITUTION:An increment/decrement instruction signal 15a is applied to one of both sides of each of AND circuits 16 - 21, and the other sides of these circuits 16 - 21 are connected to the lower 6 bits of an instruction register 14 respectively. Therefore the 11th and 13th bits corresponding to the increment signals INCA and INCB are set H levels with an instruction code in regard of the outputs of the circuits 16 - 21. Thus the circuits 16 and 18 output the signals INCA and INCB of H levels. The outputs of both circuits 16 and 18 are connected to the up-count terminals of an accumulator R1A and a B register R1B, and the data are increased in both registers R1A and R1B. As a result, both increment and decrement instructions are carried out in a single step.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a microprocessor with high-speed data processing functionality. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of the main parts of a conventional microprocessor. In the figure, R(RA) is an accumulator as register R, R(RB) is also a B register, R(RX) is an index register, and R(
RTI, RT2) are the same (temporary registers. DB is a data bus, and ALU is an arithmetic logic unit. In conventional microprocessors, increment and decrement instructions for each register R are executed by the hardware shown in Figure 3. As an example, to explain the movement of data when executing an increment instruction for accumulator RA, the first step is to change the data of accumulator RA (for example, "13").
) is output onto data bus B. As a second step, temporary register RTI stores data 113'' on the data bus. At the same time, temporary register RT2 stores a signal I which is an increment command.
NC is input and ``1'' is input as data. As a third step, the output of data "13" from accumulator RA to data bus DB is stopped, and data "13" in temporary register RTI and data "1" in temporary register RT2 are output from arithmetic logic unit ALU.
The added data "14" is output onto the data bus DB. As the fourth step, the data “14” on the data bus DB is
” is stored in accumulator RA, and arithmetic logic unit A
Stops LU data output. The operation when this increment instruction is executed is B register RB. The same applies to index register RX. Regarding the movement of data when the decrement instruction is executed, during the execution of the increment instruction, the decrement signal DEC is sent to the temporary register RT2 in the second step.
is input, "1" is entered as data, and in the third step, the arithmetic logic unit (ALU) stores the temporary register R.
The operation is the same as the increment instruction execution operation described above, except that the data "1m" in the temporary register RT2 is subtracted from the data in TI, and the subtracted data is output onto the data bus DB.

[Problem to be solved by the invention]

The increment and decrement instructions in a conventional microprocessor each require four steps of cycles (time) as described above, and the data bus DB and the arithmetic logic unit (ALU) are used each time the above instructions of the Lugistor are executed. Therefore, (from an actual assembler program, the above instructions for each register are used frequently, and the above instructions for different registers are often used consecutively), the above instructions for multiple registers at the same time The problem is that the command cannot be executed. Therefore, it is an object of the present invention to provide a microprocessor that can solve this problem.

[Means to solve the problem]

In order to solve the above problems, the microprocessor of the present invention "inputs a data input signal (DI, etc.) to input data on a data bus (DB, etc.), and inputs a data output signal (Do, etc.)." A plurality of registers that input data and output internal data to the data bus, and an increment signal (INO, etc.) generated by decoding an instruction.
and a decrement signal (such as DEC), and is provided with a register (such as R1) that simultaneously increments and decrements internal data between the corresponding registers.

[For use]

The function of an up/down counter is added to the registers in the microprocessor, and all the registers that input the decoding signal of the instruction to perform this up/down are simultaneously amplified/downed by data "1". It was designed to allow

[Example 1] The present invention will be described in detail below based on FIGS. 1 and 2. FIG. 1 shows the main structure of an embodiment of a microcomputer according to the present invention. In the same figure, R1 (RIA,
RIB, RIX) are new registers such as an accumulator, a B register, and an index register, respectively. These registers RIA, RIB, and RIX each receive data input signals DI (DIA, l1
The data on the data bus DB can be input and stored by inputting the data output signal D○ (DOA
, DOB, DOX) and outputs its own data onto the data bus DB, it also has the function of an up/down counter as described below. That is, each register RIA, RIB, RIX receives an increment signal TNC (INCA, INCB, INCX), adds 1# to its own data, and similarly receives a decrement signal DEC (DECA, DBC).
B, DECX) and subtracts “l” from its own data. In FIG. 1, 14 is a 16-bit instruction register into which 6-bit program data (instruction code) is input, and 15 is a decoder that decodes the instruction code portion (upper 10 bits) in this register 14. , 16-21 are increment/decrement command signals 15a as output signals of the decoder 15.
and input the instruction register 1.
This is an AND circuit that inputs data of each bit of the lower 6 bits of 4. AND circuits 16, 18, and 20 output increment signals rNcA, INCB, and INCX for each register RIA, RIB, and RIX, and similarly, AND gates 17, 19, and 21 output increment signals rNcA, INCB, and INCX for each register RIA, respectively. Decrement signal DECA for RIB, RIX
. Outputs DECB and DECX. FIG. 2 shows an example of the data structure of an instruction code (16 bits long) for an increment/decrement instruction. In the figure, the upper 10 bits of data "11"
01101011" is an instruction code indicating that it is an increment/decrement instruction, and the 11th instruction from the upper
The data of bits to 16th bits are AN in Figure 1.
The data input to D circuits 16 to 21 are sequentially increment/decrement signals INCA, DECA, IN.
Compatible with CB, DECB, INCX, and DECX. In this example, only the 11th and 13th bits are “1”.
”, the increment signals INCA, INC
In other words, accumulator R1^ for outputting B
This indicates that this is an instruction for incrementing the B register RIB and the B register RIB. Next, the operation when FIG. 1 executes the instruction shown in FIG. 2 will be explained. A microprocessor is run by a program. The program data shown in FIG. 2 is stored in the instruction register 14 from a ROM (not shown). In this example, the top 10
Since the bit "1101101011" is an increment/decrement instruction code, the instruction decoder 15 decodes this instruction code, recognizes it as an increment/decrement instruction, and outputs an increment/decrement instruction signal 15a as an H level. The signal 15a is connected to one of the AND circuits 16-21, and the other of the AND circuits 16-21 is connected to the lower 6 bits of the instruction register 14, respectively. Therefore, the output of the above AND circuit is the increment signal INCA using the instruction code shown in Figure 2.
, INCB are at H level, AND circuits 16 and 18 output increment signals INCA and rNcB at H level. The outputs of the AND circuits 16 and 18 are connected to the up-count terminals of the achievator RIA, the B register RIB, and the data in each register is incremented. In this way, according to the present invention, increment/decrement instructions can be executed in one step. According to the present invention, each microprocessor inputs the data input signal DI to input data on the data bus DB, and inputs the data output signal DO to transfer internal data to the data bus DB. A plurality of registers are provided, each of which receives an increment signal INC and a decrement signal DEC obtained by decoding an instruction, and includes a register R1 which simultaneously increments and decrements internal data between the corresponding registers. As a result, increment and decrement instructions for each register can be executed simultaneously in one step, enabling high-speed processing.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main part configuration as an embodiment of the present invention, Fig. 2 is a diagram showing the structure of the instruction code of the increment/decrement instruction, and Fig. 3 is the main part structure of a conventional microprocessor. FIG. R1 (RIA, RIB, RIX): L/
Register (RIA: accumulator, RIB: B register, RIX: index register), DB: data bus, 14: instruction register, 15: decoder, 16 to 21: AND circuit, INC (INCA, I
N.C.B. INCX): Increment signal, DEC (DECA,
DECB, DECX): Decrement signal, DI (
DIA, DIB, DIX): Data input number, Do (D
OA, DOB, DOX) Knee F'-Taka signal.

Claims (1)

[Scope of Claims] 1) A plurality of registers each inputting a data input signal to input data on a data bus, and inputting a data output signal to output internal data to the data bus. , a microprocessor comprising registers that input increment signals and decrement signals obtained by decoding instructions, and simultaneously increment and decrement internal data between the registers, respectively;