JPS63245522A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the size of a used microprogram by operating a logic switching means in accordance with the output of an instruction code decoder to select a register of a data or instruction queue. CONSTITUTION:A signal S from an instruction code decoder 10 is set to '0' if the register name of a register as the object is held in an instruction register 1, and the signal S is set to '1' if the register as the object is an instruction queue register 8 in which following instruction codes are held. When the signal S is '0', a register select code decoder 6 selects data registers 7a-7d by the logic switching means consisting of AND circuits 11 and 12 and an indication is given; and when the signal S is '1', the instruction queue register 8 is selected and an indication is given. Consequently, it is unnecessary to give the indication concerning the register as the object on the microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a microprocessor, and particularly to a microprocessor that operates using a microprogram.

(Prior Art) In a microprocessor that operates using a microprogram, when various instructions (for example, transfer instructions) are given to registers, it is necessary to determine where the data for specifying the register to be instructed is held. , must be specified in the microprogram. For example, in an 8-bit microprocessor, one unit length instruction code is 8 bits, so if all transfer instructions can be expressed with one unit length of 8 bits, one transfer instruction can be expressed with one unit length instruction code. can be expressed. An example of this would be a transfer from a specific data register to an accumulator. On the other hand, if the instruction code cannot be expressed using one unit length instruction code, one transfer instruction must be expressed using a plurality of unit length instruction codes. An example of this is when a constant in a program is transferred to an accumulator. In the former example, the target register name is held in the instruction register, but in the latter example, the target register is an instruction queue register that holds the subsequent instruction code. Therefore, in conventional microprocessors, these specifications are made in the microprogram.

(Problems to be Solved by the Invention) Instructions for specifying a target register are not limited to transfer instructions as in the above example, but there are many addition instructions, subtraction instructions, and so on. Therefore, in the past, instructions regarding the target registers were given on the microprogram for all these instructions, which resulted in the problem of an increase in the size of the microprogram.

Therefore, an object of the present invention is to provide a microprocessor that can reduce the size of the microprogram used as much as possible.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides an instruction register that holds an instruction code of one unit length, an instruction code decoder that decodes the instruction code in this instruction register, and an instruction code decoded by the instruction code decoder. A microprogram ROM that stores an instruction processing unit that executes instructions and a microprogram that generates microcode according to the instruction code.
I, a microcode decoder that decodes the microcode generated in this microprogram ROM section, and a microcode decoder that decodes the microcode generated in the microprogram ROM section; a register selection code decoder that selects a data register and gives an instruction based on the register name stored in the instruction register; A function that outputs the first logic when the instruction is decoded, and the second logic when the instruction for the data of the instruction code that follows the instruction code held in the instruction register is decoded. is applied to the instruction code decoder, and when the instruction code decoder is outputting the first logic, an instruction for the data register is given to the register selection code decoder, and when the instruction code decoder is outputting the second logic, the instruction for the data register is given. The system further includes logic switching means for giving an instruction to an instruction queue register holding an instruction code.

(Function) According to the microprocessor according to the present invention, when the target register name is held in the instruction register, the first logic is output from the instruction code decoder, and the target register is stored in the subsequent instruction code. When the instruction queue register holds , the second logic is output from the instruction code decoder. Then, by the function of the logic switching means, when the first logic is output, the register selection code decoder selects the data register and gives an instruction, and when the second logic is output, the register selection code decoder selects the instruction queue register. This makes it possible to give instructions.

Therefore, it is no longer necessary to give instructions regarding the target register on the microprogram, and the size of the microprogram used can be reduced.

(Example) The present invention will be described below based on an illustrative example. In order to make the features of the microprocessor according to the present invention more clear, the configuration and operation of a conventional general microprocessor will first be briefly explained. FIG. 2 is a block diagram showing an example of the configuration of a conventional microprocessor. This figure shows an instruction register 1 that holds an instruction code 1 of one unit length, an instruction code decoder 2 that decodes the instruction code in this instruction register 1, and an instruction that executes the instruction decoded by this instruction code decoder 2. Instruction processing unit 3 and microcode M according to instruction code ■
A microprogram ROM unit 4 that stores a microprogram to generate the microprogram, a microcode decoder 5 that decodes the microcode M generated in the microprogram ROM unit 4, and a microcode decoder 5 that decodes the microcode M generated in the microprogram ROM unit 4; When an instruction is given, a register selection code decoder 6 selects a data register based on the register name I2 held as part of the instruction code I in the instruction register 1 and gives an instruction.
, a data register 7 (registers A to D, A register is an accumulator) that receives instructions from this register selection code decoder 6, an instruction queue register 8 that holds the subsequent instruction code, and data is input and output from each register. A data bus 9 is shown.

Now, 1 byte (1 unit length) as shown in Figure 3(a)
A transfer instruction code consisting of
A description will be given of how each instruction is executed by the microprocessor shown in FIG. 2 with respect to a transfer instruction code consisting of bytes. Figure 3(a) shows the MOVB
-A In other words, it indicates an instruction code for transferring data in the B register 7b to the A register 7a (accumulator), and is composed of a 5-bit operation code and a 3-bit register name. This operation code indicates an instruction to transfer data from a specific data register 7 to an accumulator, and the register name in this example is the name of the B register. On the other hand, Fig. 3(b)
C. MOV69 → A, that is, constant 69 is set to A register 7.
The instruction code to be transferred to a is shown. In this case, since 1 byte is used to represent the constant 69, the instruction code is 2 bytes in total.

The microprogram ROM section 4 stores microprograms corresponding to each instruction code. Therefore, for example, as instruction code 1, MOVB-A
When the code M shown in FIG. 4(a) is given, the microcode decoder 5
When a code MOV 69→A is given, a microcode M as shown in FIG. 4(b) is given to the microcode decoder 5. Each of the microcodes M is made up of data in a plurality of fields, the first field being data related to the transfer source, and the second field being data related to the transfer destination. The transfer destinations all indicate the A register. The signal 2 generation code and the signal 9 generation code indicating the transfer source are data that cause the microcode decoder 5 to generate the signal P and signal Q, respectively, and the signal P indicates that the transfer source is one of the data registers 7a to 7d. The signal Q indicates that the transfer source is the instruction queue register 8.

The instruction code l applied to the instruction register is decoded by the instruction code decoder 2, and the instruction is executed by the instruction processing section 3 with the addition of a signal from the microcode decoder. Register 8 summer 2 of instruction code I is given to register selection code decoder 6. Therefore, when an instruction code I such as MOVB-A as shown in FIG. 3(a) is given, the register selection code decoder 6 is given 3-bit data indicating register B. At this time, since the microcode decoder 5 is given the microcode M as shown in FIG. 4(a), the microcode decoder 5 outputs the signal P.
only occurs. Register selection code decoder 6 receives this signal P and selects and designates one of the data registers 7. In this example, the register name ■2 indicates register B, so data register 7b is selected and specified.
In response to this designation, data register 7b outputs the held data to data bus 9. Furthermore, since the second byte of the microcode M indicates that the transfer destination is the A register, the A register receives the selection instruction from the register selection code decoder 6 and takes in the data on the data bus 9. . As described above, MOV B→A is executed.

On the other hand, when an instruction code I as shown in FIG. 3(b) is given, the operation code of the first byte is all given to the instruction code decoder 2 and decoded. At this time, the microcode decoder 5 is
), the microcode decoder 5 generates only the signal Q. Therefore, register selection code decoder 6 does not select and designate data register 7 as a transfer source.

Since the signal Q specifies the instruction queue register 8, one byte of the next instruction code held in the instruction queue register 8, that is, the constant 69 of the second byte in FIG. 3(b), is transferred to the data bus 9. It is output and taken into the A register. As described above, MOV 69→A is executed.

The configuration and operation of a conventional microprocessor has been explained above, but as shown in Figure 4, separate microcodes must be prepared for various instruction codes, so there is a problem that the size of the microprogram becomes large. As already mentioned, there are some points. Therefore, the present invention has solved this problem with the following configuration.

FIG. 1 is a block diagram showing the configuration of a microprocessor according to an embodiment of the present invention. Here, the same components as those of the conventional device shown in FIG. 2 are designated by the same reference numerals, and the explanation thereof will be omitted. A characteristic feature of this device is that the instruction code decoder 10 outputs a signal S, and this signal S
This is the point given to two AND circuits 11 and 12. These two ANDiffi paths 11, 12 constitute a logic switching means and output only either the signal R or the signal T.

When the instruction code decoder 10 decodes an instruction to a register corresponding to the register name held in the instruction register 1, that is, when it decodes an instruction code as shown in FIG. 3(a), When a logic "0" is output and an instruction for the data of the instruction code following the instruction code held in the instruction register 1 is decoded, the instruction code as shown in FIG. 3(b) is output. When decoded, outputs logic "1". AND
Since the human logic on the signal S side of circuit 11 is inverted,
When the signal P is output from the microcode decoder 5, when the signal S is logic "01", the signal R is output, and when the signal S is logic "1", the signal T is output. Become.

Now, as shown in Figure 3(a), MOVB-A
Considering the operation when the instruction code ■ is input, operation code 11 is input to instruction code decoder 1.
0, register name I2 is register selection code decoder 6
will be given to each. Here, since the instruction code decoder 10 outputs logic "0" as the signal S, if the signal P is output, the signal R is given to the register selection code decoder 6, and the register I2 is set to B.
Since this indicates a register, the register selection code decoder 6 selects and specifies the B register, and the contents of the B register are output to the data bus 9 and transferred to the A register.

On the other hand, as shown in FIG. 3(b), MOV 69→A
Considering the operation when instruction code 1 is input manually, all the operation codes of the first byte are given to the instruction code decoder 10.

Here, the instruction code decoder 10 outputs a logic signal "S" as a signal S.
1”, so if signal P is output,
Signal R is not applied to register selection code decoder 6, but signal T is applied to instruction queue register 8. Therefore, the contents of the instruction queue register 8, that is, the constant data of the second byte shown in FIG. 3(b), are output to the data bus 9 and transferred to the A register.

Now, considering the signal P, it is sufficient that the signal P is output in the case of either of the above-mentioned transfer commands. In other words, there is no need to change the signal P for the two transfer commands mentioned above. As shown in Figure 5, this also applies to the transfer command MOVA-4B.
Both transfer commands 69→A indicate that microcode M that generates signal P is used for the transfer source. In the conventional device, it was necessary to generate separate microcodes M as shown in FIG. 4, but in the present device, there is no such need.

The operation of the microprocessor according to the present invention has been described above using two transfer instructions as examples, but the present invention is effective not only for transfer instructions but also for various instructions such as addition and subtraction. Therefore, it becomes possible to considerably reduce the size of the microprogram in the microprogram ROM 4.

〔Effect of the invention〕

As described above, according to the microprocessor according to the present invention, when the target register name is held in the instruction register, the first logic is output from the instruction code decoder, and the target register reads the subsequent instruction code. When the instruction queue register is being held, the second logic is output from the instruction code decoder, and by the function of the logic switching means, when the first logic is output, the register selection code decoder selects the data register. This makes it possible to select the instruction queue register and give instructions when the second logic is being output, so there is no need to give instructions regarding the target register on the microprogram. It becomes possible to reduce the size of the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional microprocessor, and FIG. 3 is a diagram showing an example of a general instruction code. , FIG. 4 is a diagram showing an example of a microcode in a conventional device, and FIG. 5 is a diagram showing an example of a microcode in a device according to the present invention. 1...Instruction register, 2...Instruction code decoder,
3...Instruction processing section, 4...R for microprogram
OM section, 5... Microcode decoder, 6... Register selection code decoder, 7a to 7d... Data register, 8... Instruction queue register, 9... Data no(s), 10... Instruction Code decoder, 11...A
ND circuit, 12...AND circuit, I...instruction code, I1...operation code, I2...register name, M...microcode, P, R, S, T...
logical signal. Applicant's agent Sato - Recommendation Figure 1 Figure 2

Claims (1)

[Claims] An instruction register that holds an instruction code of 1.1 unit length;
It stores an instruction code decoder that decodes the instruction code in this instruction register, an instruction processing unit that executes the instructions decoded by this instruction code decoder, and a microprogram that generates a microcode according to the instruction code. a microprogram ROM section, a microcode decoder that decodes the microcode generated in the microprogram ROM section,
a register selection code decoder that selects and issues an instruction to a data register based on a register name held as part of an instruction code in the instruction register when an instruction to a register is given from the microcode decoder; In a microprocessor, when an instruction to a register corresponding to a register name held as part of an instruction code in the instruction register is decoded, a first logic is set in the instruction register. The instruction code decoder is provided with a function of outputting a second logic when an instruction for data of an instruction code following an instruction code is decoded, and the instruction code decoder outputs the first logic. Logic that provides an instruction to the data register to the register selection code decoder when the instruction code decoder is outputting a second logic, and provides an instruction to the instruction queue register holding the subsequent instruction code when the instruction code decoder is outputting a second logic. A microprocessor further comprising switching means. 2. An instruction code that gives a transfer instruction to the register corresponding to the register name held as part of the instruction code in the instruction register, and an instruction code that follows the instruction code held in the instruction register. The microprocessor according to claim 1, wherein the microprogram ROM section generates the same microcode for two instruction codes: an instruction code for giving a transfer instruction for data; . 3. The microprocessor according to claim 1 or 2, wherein instructions for each register are instructions for transfer, addition, and subtraction. 4. The microprocessor according to any one of claims 1 to 3, wherein the logic switching means is comprised of a logic gate circuit. 5. The logic switching means is composed of two AND circuits,
The first AND circuit receives as input the third logic indicating the existence of an instruction for the register from the microcode decoder and the first logic from the instruction code decoder. The third logic from the code decoder and the second logic from the instruction code decoder are given as inputs, the logic output of the first AND circuit gives an instruction to the register selection code decoder, and the second logic 5. The microprocessor according to claim 4, wherein an instruction is given to the instruction queue register by the logical output of the AND circuit.