JPS6151242A - Instruction decoding circuit - Google Patents

Abstract

PURPOSE:To execute an underfined instruction not decoded by a decoder but set by the operator as a macroinstruction by allowing the operator to write the macroinstruction to plural registers and designating the selected order. CONSTITUTION:When the operator executes an instruction not in a processor, the operator writes a control sequence to registers 7-10 for setting macroinstruction by using a program and when a decoder 24 decodes this sequence, the control is effective. The registers 7-10 are designated by the operand of the macroinstruction or selected by the cycle number of the macroinstruction. That is, the operator writes a macroinstruction to the registers 7-10, and the order selecting the registers 7-10 and the number of cycles operated in response to the content of the registers are designated to a logical arithmetic unit 4. Thus, the undefined instruction set by the operator not decocded by the decoder 24 is executed as the macroinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for decoding instructions for controlling a logical arithmetic unit of a real-time processor, and in particular for a circuit for decoding instructions set by an operator to be executed on the logical arithmetic unit. The present invention relates to an instruction decoding circuit capable of decoding instructions.

Real-time processing processors are used in various communication devices and electronic devices, and perform various functions according to programs. The logical operation unit then performs operations on the operands according to instructions decoded and sent by the decoder.

In this case, if the operator considers that the program will be shorter if there is a certain instruction, it is possible to set that instruction, and cause the logical operation unit to execute that instruction in addition to the instructions instructed by the decoder. If possible, the processing efficiency of the processor can be improved.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional instruction decoding circuit.

When the decoder 1 decodes an instruction and stores data from the data bus 6 in the register 2, the decoder 1 uses an enable signal AEN.
Send out. Furthermore, when storing data from the data bus 6 in the register 3, an enable signal BEN is sent.

Depending on the content of the command, the decoder 1 instructs the logical operation unit 4 to perform the following functions, for example, using signals cl, C2, and C3. That is, the function instruction signal C+.

If the data stored in register 2 is A when both C2 and C3 are "0", A is sent out as is.

If C, , C2 are "0" and 03 is "1" and the data stored in register 3 is B, B is sent out as is.

When C3 is "0" and 02 is "P1", data 8 in register 2 is operated and -A is sent out.

When C1 is 0'' and C2 and C3 are 1, data B in register 3 is operated and -B is sent out.

When C, is "1" and C2, C3 are "0", data A in register 2 and data B in register 3 are operated and the logical product A-B is sent out.

c,, When C3 is "1" and 02 is "0", calculate the logical sum AVB by calculating data A of register 2 and data B of register 3.
(The symbol ■ represents a logical sum).

When C2 is "1" and C3 is "0", data A in register 2 and data B in register 3 are operated and A+B is sent out.

When c, , C2, and C3 are both '1', data A in register 2 and data B in register 3 are operated and A-B is sent out.

The output of the logical operation unit 4 is stored in the register 5 using the enable signal DEN sent from the decoder 1.

[Problem that the invention seeks to solve]

As mentioned above, the decoder of the conventional instruction decoding circuit is constituted by a logic circuit, and there is a problem in that it does not have a function where an operator sets an instruction and causes the logic operation unit to execute the instruction.

[Means for solving problems]

The above problem consists of a plurality of registers for setting macro instructions, a selection means for selecting the registers, and a means for sending the contents of the register selected by the selection means to the logical operation unit instead of the instruction sent by the decoder. The problem is solved by providing the decoder, selecting the register, and outputting a macro instruction to be executed by the logical operation unit.

[Effect]

In other words, the operator can write macro instructions into multiple registers, and specify the order in which the registers are selected and the number of cycles for the logical operation unit to operate according to the contents of the registers. This allows commands that cannot be executed by the system to be executed at any time.

In other words, an undefined instruction set by an operator that cannot be decoded by a decoder can be executed as a macro instruction.

Embodiment C FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention.

In FIG. 1, numerals 2 to 6 correspond to those in FIG. The normal operation of the decoder 24 is the same as that shown in FIG.
enable signals AEN, BEN;

DEN and function instruction signals c, .

When the operator executes an instruction that is not available in the processor, the operator writes a control sequence into macro instruction setting registers 7 to 10 by a program, and the control becomes effective when the decoder 24 decodes this sequence. Registers 7-10 are specified by the operands of the macroinstruction or selected by the cycle number of the macroinstruction.

That is, for example, when writing MACROa, b in assembler language, a indicates the first register number of registers 7 to 10 from which the control sequence is read and the order of the following registers, and b
indicates the number of control cycles.

If this is written as MACROI, 1, control is performed by the sequence of register 7, and it is a one-cycle instruction.

Also, when written as MACRO2 and 3, it is a 3-cycle command where the control of the cycle 1 is performed by the sequence of register 8, the control of the 2nd cycle is performed by the sequence of register 9, and the control of the 3rd cycle is performed by the sequence of register 10. It turns out that.

Also, when written as MΔCR○1,3, the first cycle is controlled by the sequence of register 7, the second cycle is controlled by the sequence of register 8, and the third cycle is controlled by the sequence of register 9.3 cycles. This means that it is a command.

For example, set 111101 in register 7, and
The operation when CROI is written as 1 will be explained. Decoder 24 sends a 2-bit code to selector 11, selects register 7, and sends "1" to MA.

From selector 11, 111101 of register 7 is ANDed.
are sent to circuits 12-17, respectively, and AND circuits 12-15.
Each output of the AND circuit 16 is “1” and the output of the AND circuit 16 is “0”.
The output of the ND circuit 17 becomes "1".

Therefore, the data stored in registers 2 and 3, for example AI and B1, is 0 when Cl and C2 are 1'' in the logical operation unit 4.
Since 3 is 0”, AI +81
, are stored in the register 5, data A2 of the data bus 6 is stored in the register 2, and data B2 is stored in the register 3, respectively.

In this embodiment, registers 7 to 10 for setting macro instructions are set to 4.
Although this number has been explained in terms of number, this number can be set arbitrarily.

〔Effect of the invention〕

As explained above, according to the present invention, an operator can set a macro instruction that is not originally defined and cannot be decoded, and cause the logical operation unit to execute it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional instruction decoding circuit. In the figure, 1.24 is a decoder, 2.3, 5.7 to 10 are registers, 4 is a logical operation unit, 11 is a selector, 12 to 17 are AND circuits, and 18 to 23 are OR circuits.

Claims (1)

[Claims] A circuit for decoding instructions for controlling the operation of a logical arithmetic unit includes a plurality of registers for setting macro instructions, a selection means for selecting the registers, and an instruction for a decoder to send out the contents of the registers selected by the selection means. An instruction decoding circuit characterized in that the instruction decoding circuit is further provided with means for sending data to a logic operation device instead, and causes the decoder to select the register and instruct the logic operation device to perform an operation on the contents of the register.