JPS60246439A - Information processor - Google Patents

Abstract

PURPOSE:To generate an instruction address at a high speed by adding ''1'' to the contents of an address register means in case when an instruction to be executed in the next time is the next address of an instruction which has been executed before said instruction. CONSTITUTION:An operation controlling circuit 27 of a main storage device 2 receives data by an address register 21, inputs its data to an instruction address register 23 at the time point when an instruction of read of an instruction has been received, adds ''1'' to the data by operating an adding circuit 24 and holds it. In case the last processing of the inputted instruction is ended, and with respect to an intruction whose execution is desired, it does not occur that the instruction address jumps due to a branch instruction, etc., a controlling circuit 13 of a central processor 1 gives immediately an instruction of a +1 instruction request to the main storage device 2 through a command bus 5. The controlling circuit 27 gives the data of the instruction address register 23 to a decoder 22 through a gate G2, and an instruction stored in a memory circuit 26 is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus, and particularly to an information processing apparatus that sequentially reads instructions stored in a main memory and executes a process fM.

(Prior Art) Conventionally, a central processing unit and a main memory fL! In an information processing device configured with an information processing device, when instructions stored in the main memory are sequentially read and processed, a program counter is provided in the central processing unit to indicate the location of the instructions to be executed. First, the contents of the program counter are sent to the main memory, and the main memory reads the instructions to be executed. The central processing unit then takes the read instruction and places it in the instruction register. Then, the read instruction is decoded and the processing specified by the instruction is performed. Normally, the next instruction to be executed is read from the address following the instruction that has just been executed, so 1 is added to the contents of the program counter and the above operation is repeated again. In addition, in the case of a branch instruction, the instruction address determined by the processing result is sent to the main memory kK, and the contents of the program counter are rewritten to this instruction address.
(Problem to be solved by the invention) General programs have relatively few branch instructions,
In many cases, the instruction is at the next address. Therefore,
If the next instruction address is created in the central processing unit each time and sent to the main memory, processing time is required, which has the disadvantage that the processing capacity cannot be increased accordingly.

(Means for resolving the inter-group point) In order to solve the above-mentioned inter-group point, the present invention creates the address of the next instruction in the main memory, and sends the address from the central processing unit to +
It is an information processing device designed to shorten the time it takes for the central processing unit to obtain instructions and improve its processing ability by reading nine instructions upon receiving an instruction requesting one instruction. In the information processing system kic, in which the central processing unit sequentially escapes instructions stored in the main memory and executes processing, the address of the instruction is stored in the main memory control unit that controls the main memory 1/l. instruction address register means; addition means for adding 1 to the contents of the instruction address register means after outputting the instruction to the main memory control section; an indulgence means for reading out the instruction at the address held by the instruction address register means; and, if the next instruction to be executed by the central processing unit is the next address of the executed instruction, requesting the +1 instruction from the main memory; +1 command requesting means for instructing.

(Embodiment) FIG. 1 is a professional diagram of an embodiment of the present invention, in which a central processing unit (CPU) 1 and a main memory device fi (MEM) 2 are connected to an address bus 3, a data bus 4, and a command bus. 5 and K are connected. In the figure, only the portions of the central processing unit 1 and the main storage device 2 that are necessary for explaining the present invention are shown, and other commonly provided functional blocks are not shown. Central processing unit &1 has A path (A-B) and B bus (B-B) for transferring data.
and a C-bus (C-B), and an arithmetic circuit (C-B) that receives input from the human bus and the B-path and outputs to the C-bus.
ALU)11. Receives input from C bus and sends it to A bus or B
A register (IG) 12 that outputs to the bus, an instruction register (IR) 14 that receives input from the B bus and outputs to the control circuit (CONT) 13. Also shown is an instruction address register (L) 15 that receives input from the C bus and outputs it to the B bus. Data can be transferred to bus 4. The control circuit 13 also controls the central processing unit, including functional blocks not shown. Next, the main memory device a2 includes an address register (ADR) 21 that receives input from the address bus 3 and sends an output to the decoder circuit (DCD) 22 via the gate circuit G1. The instruction address register (IADR) 23 sends the output obtained by adding 1 by the adder circuit (+1) 24 to the decoder circuit 22 via the gate circuit G; ) 25, and an operation control circuit (CONT) 27 that controls the functional blocks of the main memory according to instructions received from the central processing unit 1 via the command bus. It is shown.

Next, the operation of this embodiment will be explained. First, when an instruction address is set in the instruction address register 15 of the central processing unit fi11, the control circuit 13 is transferred to the main memory fii2 via the B bus and the address bus 3. At the same time as sending this data to the address register 21, the control circuit 13 sends an instruction to read the instruction to the operation control circuit 27VC of the main storage device 12 via the command bus 5. The operation control circuit 27 sends the data of the address register 21 to the decoder 22 via the gate G1.
Then, the instruction stored in the memory circuit 26 is read out and transferred to the buffer register 25. The oil j control circuit 13 of the central control unit (112) waits a certain period of time for the instruction to be read after sending the read instruction, and then transfers the instruction from the buffer register 25 to the instruction register II via the data bus 4 and the B path.
Take in C. Next, the control circuit 13 executes the fetched instruction, but the operation control circuit 27 of the main memory device 2 receives the data in the address register 21, and upon receiving the instruction to read the instruction, transfers the data to the instruction address. register 2
3 and operates the adder circuit 24 to add 1 to the data and hold it. On the other hand, the control circuit 1 of the central processing unit [1]
3, when the last processing of the fetched instruction is completed and the executed instruction is a branch instruction etc. and the instruction address does not jump, a +1 instruction request is immediately sent to the main storage device 2 via the command bus 5. Send instructions. In response to this instruction, the control circuit 27 of the main memory device 12 supplies the data of the instruction address register 23 to the decoder 22 via the G, and reads out the instruction stored in the memory circuit 26 as before. and is stored in the buffer register 25. The following operations are performed in the same way as before. Note that, after sending out the +1 instruction request, the control circuit 13 of the central processing unit 1 increments the contents of the instruction address register 15 by +1 to clarify the instruction address being executed. When reading an instruction at an address specified by a branch instruction or the like, the determined address data is stored in the selected address register 15, and the instruction is read by the method described at the beginning.

(Effects of the Invention) As explained above in detail, the present invention creates the address of the next instruction to be executed after the completion of execution of the instruction in the conventional central processing unit, sends this address to the main memory, and then executes the instruction. If the instruction is to be read from the next address, the next instruction will be read simply by issuing a +1 instruction request instruction from the central processing unit. When available, it has the effect of improving the efficiency of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Central processing unit 1 (CPU), 2...
・・Main memory (MBM), 3, 4, 5. A-B, B
-B, C-B... Bus, 11... Arithmetic circuit (ALU), 12... Register (几EG)
, 13... Control circuit (CONT) 14...
...Instruction register (IR), 15...Instruction address register (LR), 21...Address register (ADR), 22...Decoder (DCD), 2
3...Instruction address register (IADR), 2
4...+1 addition X circuit (+1), 25...
・Buffer register (BR), 26... Memory circuit (MM), 27... Operation control circuit (CON
T), G,, G,...Gate circuit.

Claims (1)

[Scope of Claims] In an information processing device 1llc in which a central processing unit sequentially reads instructions stored in a main memory and executes processing, a main memory control unit that controls the main memory stores an address of a trap instruction. instruction address register means for
addition means for adding 1 to the contents of the instruction address register means after reading an instruction to the Shinto; and an instruction at an address held by the instruction address register means upon receiving a +1 instruction request instruction from the central processing unit to the main memory control unit. and +1 instruction requesting means for instructing the central processing unit iK to request the +1 instruction from the main memory fiK if the next instruction to be executed is the next address of the previously executed instruction. Information processing equipment jlL with this as a % characteristic.