JPS5856027A - Conditional relational operating device - Google Patents
Conditional relational operating deviceInfo
- Publication number
- JPS5856027A JPS5856027A JP15500281A JP15500281A JPS5856027A JP S5856027 A JPS5856027 A JP S5856027A JP 15500281 A JP15500281 A JP 15500281A JP 15500281 A JP15500281 A JP 15500281A JP S5856027 A JPS5856027 A JP S5856027A
- Authority
- JP
- Japan
- Prior art keywords
- conditional
- result
- comparison
- gate
- comparison result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は条件付比較演算命令を実行する装置。[Detailed description of the invention] The present invention is an apparatus for executing a conditional comparison operation instruction.
例えばベクトルプロセッサ等の演算装置に関し、処理速
度の向上を計ったものである。For example, it is intended to improve the processing speed of arithmetic devices such as vector processors.
例えばベクトル演算命令の一つにも条件付比較演算命令
がある０
これはベクトルオペラントム１、Ｂ１の大小を比較し、
例えばＡ１≧Ｂ１であればＣ１−”ｌ”とし、Ａｉ＜Ｂ
ｉであればｃｉ−＠ｏ”とするような比較命令（但しｉ
−１，２ｓ３＋・・・・・・・・・ｎ）に対して、さ
らにマスクデータ（条件） Ｍｉ’ｉｉ付加し、Ｍｉ−
＠ｌ’のときは上記の比較を行ない、Ｍｌ−′″Ｏ″の
ときには比較を行なわないようにして、１ｔ−１−ｎｔ
で変化すせてｎ個のエレメント・データについて演算を
行なわせるものである。For example, one of the vector operation instructions includes a conditional comparison operation instruction. This compares the magnitude of vector operants 1 and B1,
For example, if A1≧B1, set C1-“l”, and Ai<B
If i, then ci-@o” is the comparison command (where i
-1,2s3+......n), further add mask data (condition) Mi'ii, and Mi-
When @l', perform the above comparison, and when Ml-'''O'', do not perform the comparison, and 1t-1-nt
This allows calculations to be performed on n element data.
従来はＭｉ−＠Ｏ”の場合には、実際に比較演算そのも
の全行なわない方式と、比較演算は行なってもその結果
ｔ０１に書込まないようにする方式とがあるが、いずれ
の場合にもＣ１の値は保証されていないことになる。Conventionally, in the case of ``Mi-@O'', there are methods that do not actually perform the comparison operation at all, and methods that perform the comparison operation but do not write the result to t01, but in either case, This means that the value of C1 is not guaranteed.
その０１がさらに別の条件付演算のマスクデータ狙とし
て用いられる場合には、上記のよりな０１は＠０”にし
ておく必要がある。そこで従来は条件付比較演算命令に
より得た結果Ｃ１に対し、さらに論理積命令によって（
０１・Ｍｉ）を算出する必要があった０
本発明は、一般に比較演算命令の結果は条件付演算命令
の条件部に用いられる場合が多いこと。If that 01 is used as the mask data target for another conditional operation, the above-mentioned 01 needs to be set to @0''.Therefore, conventionally, the result C1 obtained by the conditional comparison operation instruction is On the other hand, by further conjunction instruction (
In the present invention, the result of a comparison operation instruction is often used in the condition part of a conditional operation instruction.
またその比較演算命令が条件付きであってそのマスクＭ
１が１０″であったという仁とは、その比較結果０１’
ｌｉ条件にするときにも少くともその１についての演算
は不要な筈であることに鑑み、条件付比較演算命令でＭ
ｌ −’ Ｏ”のときは結果ａｔ４必らず＠ Ｑ ＩＩ
にするようにし、従来必要であった論理積処理（ａｔ・
Ｍｉ）ｔ−不要にしたものである０図は本発明の一実施
例ブロック図であり、ＭＳは主記憶装置、ＣＰＵはスカ
ラー演算及び全システムの制御を行なう中央処理装置、
その他はベクトルプロセッサを構成する部分であり、Ｖ
Ｒはベクトルレジスタ、工Ｒはベクトル命令レジスタ、
ＤＷＯ／ｆｌ命令解読器、Ｃ！ＯＭＦは比較器、Ｇ１、
Ｇ２はアンドゲート、Ｇ３はオアゲートである。In addition, the comparison operation instruction is conditional and the mask M
1 is 10'', and the comparison result is 01'
Considering that there is no need to perform an operation on at least 1 when making the li condition, we use the conditional comparison operation instruction to
When l −' O”, the result at4 is always @ Q II
, and the logical product processing (at.
Mi) t- 0 Figure is a block diagram of an embodiment of the present invention, where MS is a main memory, CPU is a central processing unit that performs scalar calculations and controls the entire system,
The other parts are parts that make up the vector processor, and V
R is a vector register, R is a vector instruction register,
DWO/fl instruction decoder, C! OMF is a comparator, G1,
G2 is an AND gate, and G3 is an OR gate.
ＩＲ中の命令のＯＰコードをデコードして比較演算命令
であれば比較器００ＭＰが起動され、ベクトルレジスタ
ＶＲからムｉ、Ｂｉ）フェッチし、その結果ｔ０１へ入
れる。The OP code of the instruction in the IR is decoded and if it is a comparison operation instruction, the comparator 00MP is activated, fetches Mui, Bi) from the vector register VR, and stores the result in t01.
ここで従来の条件付比較演算命令の場合はさらにマスク
Ｍ１も入力し、Ｍｉ−＠ｌ’の場合は比較結果’ＱＣ１
へ書込むが、Ｍｉ −” Ｏ”のときは書込み信号ｖ１
１ｉｔ−出さず、Ｃ１への曹込みは行なわず、従って０
１は出値が残っていることになる。Here, in the case of the conventional conditional comparison operation instruction, the mask M1 is also input, and in the case of Mi-@l', the comparison result 'QC1
However, when Mi − “O”, the write signal v1
1it- is not output, no addition to C1 is performed, and therefore 0
1 means that the posted price remains.
一方、本発明では条件付比較演算命令の場合でも、書込
み信号ｗｍは毎回出力し、その代りゲートＧ１−０３ｔ
″設けている。即ち条件付比較演算の場合デコーダ出力
（ＶＯ８Ｄ ）が＠１ｍになり。On the other hand, in the present invention, even in the case of a conditional comparison operation instruction, the write signal wm is output every time, and instead, the write signal wm is output at the gate G1-03t.
In other words, in the case of conditional comparison operation, the decoder output (VO8D) becomes @1m.
ゲートＧｌは閉じ、グー）Ｇ２においてはマスクＭ１が
＠１”であれば比較結果がそのまま選択され。In G2, if the mask M1 is @1'', the comparison result is selected as is.
グー）Ｇ３’ｉｉ介してＣ１に書込まれる。マスクＭ１
が＠Ｏｍのときは比較結果に係らすＧ２出力は＠０”に
なって、この値が０１に書込まれる。また条件付でない
通常の比較演算時はＶＯ８Ｄが０“となり。G) Written to C1 via G3'ii. Mask M1
When is @Om, the G2 output related to the comparison result becomes @0'', and this value is written to 01. Also, during normal comparison operation without conditions, VO8D becomes 0''.
暑
比較結果がそのままゲートＧ１％Ｇ３ｔ−介して０１に
書込まれる。The heat comparison result is directly written to 01 via the gate G1%G3t-.
以上の如く本発明では条件付比較演算命令の場合にＭｉ
−＠Ｏ’であれば結果Ｃ１も＠０”にするようにした
九め、Ｃ１ヲさらに他の条件付演算の条件付演算の条件
部に用いるときでも余分な処理が不要になり、ベクトル
演算の高速化に効果大である。As described above, in the present invention, in the case of a conditional comparison operation instruction, Mi
- If it is @O', the result C1 is also @0'', and even when C1 is used in the conditional part of another conditional operation, no extra processing is required, and vector operation This is very effective in speeding up the process.
図は本発明の一実施例ブロック図であり、ＶＲはベクト
ルレジスタ、工Ｒはベクトル命令レジスタ、ＯＯＭＦは
比較器、ＤＥＣはデコーダ、Ｇ１、Ｇ２はアンドゲート
、Ｇ３はオアゲート、ｗｍは膏込み信号である。＝The figure is a block diagram of one embodiment of the present invention, where VR is a vector register, R is a vector instruction register, OOMF is a comparator, DEC is a decoder, G1 and G2 are AND gates, G3 is an OR gate, and wm is a signal. It is. =
Claims (1)
果を出力し、条件部が偽のときはオペランド間の比較及
びその結果の出力が不要とされる条件付比較演算命令を
行なうとともに、上記比較演算結果が他の条件付演算命
令の条件部として使用されるような条件付比較演算装置
において、上記条件部が偽のときには比較結果を偽とし
て出力するようにしたことｔ特徴とする条件付比較演算
装置。When the conditional part is true, a comparison between operands is performed and the result is output, and when the conditional part is false, a conditional comparison operation instruction is executed that does not require comparison between operands and output of the result, and the above-mentioned In a conditional comparison operation device in which a comparison operation result is used as a condition part of another conditional operation instruction, when the condition part is false, the comparison result is output as false. Comparison calculation device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15500281A JPH0232663B2 (en) | 1981-09-30 | 1981-09-30 | JOKENTSUKIHIKAKUENZANSOCHI |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15500281A JPH0232663B2 (en) | 1981-09-30 | 1981-09-30 | JOKENTSUKIHIKAKUENZANSOCHI |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856027A true JPS5856027A (en) | 1983-04-02 |
| JPH0232663B2 JPH0232663B2 (en) | 1990-07-23 |
Family
ID=15596547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15500281A Expired - Lifetime JPH0232663B2 (en) | 1981-09-30 | 1981-09-30 | JOKENTSUKIHIKAKUENZANSOCHI |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0232663B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0126247A2 (en) * | 1983-05-18 | 1984-11-28 | International Business Machines Corporation | Computer system |
| JPS61262844A (en) * | 1985-05-16 | 1986-11-20 | Nec Corp | Arithmetic unit |
| FR2648928A1 (en) * | 1989-06-23 | 1990-12-28 | Peugeot | DEVICE FOR GENERATING A BIT MASKING SIGNAL DURING A DYNAMIC COMPARISON OF A SERIAL DATA FRAME, WITH A SETPOINT |
| FR2648924A1 (en) * | 1989-06-23 | 1990-12-28 | Peugeot | Device for dynamic comparison of a serial data frame, with a datum value |
| JP2015143991A (en) * | 2006-09-22 | 2015-08-06 | インテル コーポレイション | Instruction and logic circuits for processing text strings |
-
1981
- 1981-09-30 JP JP15500281A patent/JPH0232663B2/en not_active Expired - Lifetime
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0126247A2 (en) * | 1983-05-18 | 1984-11-28 | International Business Machines Corporation | Computer system |
| JPS61262844A (en) * | 1985-05-16 | 1986-11-20 | Nec Corp | Arithmetic unit |
| FR2648928A1 (en) * | 1989-06-23 | 1990-12-28 | Peugeot | DEVICE FOR GENERATING A BIT MASKING SIGNAL DURING A DYNAMIC COMPARISON OF A SERIAL DATA FRAME, WITH A SETPOINT |
| FR2648924A1 (en) * | 1989-06-23 | 1990-12-28 | Peugeot | Device for dynamic comparison of a serial data frame, with a datum value |
| US5072207A (en) * | 1989-06-23 | 1991-12-10 | Automobiles Peugeot | Device for generating a signal for one-bit masking at the time of a dynamic comparison of a mesh of serial data with a reference |
| JP2015143991A (en) * | 2006-09-22 | 2015-08-06 | インテル コーポレイション | Instruction and logic circuits for processing text strings |
| JP2015143993A (en) * | 2006-09-22 | 2015-08-06 | インテル コーポレイション | Instruction and logic circuits for processing text strings |
| JP2015143992A (en) * | 2006-09-22 | 2015-08-06 | インテル コーポレイション | Instruction and logic circuits for processing text strings |
| US9448802B2 (en) | 2006-09-22 | 2016-09-20 | Intel Corporation | Instruction and logic for processing text strings |
| US9495160B2 (en) | 2006-09-22 | 2016-11-15 | Intel Corporation | Instruction and logic for processing text strings |
| US9632784B2 (en) | 2006-09-22 | 2017-04-25 | Intel Corporation | Instruction and logic for processing text strings |
| US9645821B2 (en) | 2006-09-22 | 2017-05-09 | Intel Corporation | Instruction and logic for processing text strings |
| US9703564B2 (en) | 2006-09-22 | 2017-07-11 | Intel Corporation | Instruction and logic for processing text strings |
| US9740490B2 (en) | 2006-09-22 | 2017-08-22 | Intel Corporation | Instruction and logic for processing text strings |
| US9740489B2 (en) | 2006-09-22 | 2017-08-22 | Intel Corporation | Instruction and logic for processing text strings |
| US9772846B2 (en) | 2006-09-22 | 2017-09-26 | Intel Corporation | Instruction and logic for processing text strings |
| US9772847B2 (en) | 2006-09-22 | 2017-09-26 | Intel Corporation | Instruction and logic for processing text strings |
| US9804848B2 (en) | 2006-09-22 | 2017-10-31 | Intel Corporation | Instruction and logic for processing text strings |
| US10261795B2 (en) | 2006-09-22 | 2019-04-16 | Intel Corporation | Instruction and logic for processing text strings |
| JP2019220236A (en) * | 2006-09-22 | 2019-12-26 | インテル コーポレイション | Processor, system and method |
| US10929131B2 (en) | 2006-09-22 | 2021-02-23 | Intel Corporation | Instruction and logic for processing text strings |
| US11023236B2 (en) | 2006-09-22 | 2021-06-01 | Intel Corporation | Instruction and logic for processing text strings |
| US11029955B2 (en) | 2006-09-22 | 2021-06-08 | Intel Corporation | Instruction and logic for processing text strings |
| US11537398B2 (en) | 2006-09-22 | 2022-12-27 | Intel Corporation | Instruction and logic for processing text strings |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0232663B2 (en) | 1990-07-23 |
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