JPS61175732A - Performance control system for information processor - Google Patents

Abstract

PURPOSE:To obtain the performance of the titled processor which is coincident with the set performance by controlling the performance of an arithmetic unit in response to an arithmetic execution signal with an indication given to an arithmetic control means for the arithmetic idle processing set previously, therefore, producing an idle time to the arithmetic execution. CONSTITUTION:A register 37 holds a microinstruction read out of a control storage CS, and a decoder 38 decodes the microinstruction when a latch 32 is set (-EXB=0) to control the execution of an arithmetic unit. When a suppression signal FWAIT given from a performance control circuit is set at 1, a latch EXB32 is set at 0 for suppression of the signal FWAIT. Then the signal WAIT is sent to a latch EXC33 after half cycle and kept at '0' for a cycle. When the signal FWAIT is released, the contents '1' of a latch EXA31 are sent to the EXB32 for repetition of an operation where the signal FWAIT is delivered by a cycle when the EXB32 is delivered by two cycles. As a result, the operation is executed just in a cycle of the EXB and the arithmetic time is equal to a cycle of the signal FWAIT.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a performance control method for an information processing device.

[Background of the invention]

As a provider of information processing devices, it is important to provide information processing devices with performance that meets the demands of two different users.

The following methods have been proposed as methods for changing the processing capacity of an information processing device.

(1) A method of changing the CPU machine cycle.

(2) A method of changing the capacity of a buffer memory that holds data as a copy of the main memory and allows data to be read/written at high speed.

(3) In large-scale computers that employ pipeline control, a method is provided in which the advance control section has idle time for each instruction (Japanese Patent Application No. 56-92341).

In the method (1), the range in which the machine cycle can be varied is different for each device, and the variable range is small, and problems with machine reliability arise due to changes in the machine cycle.

In the method (2), it has little effect on the performance of individual programs, so it is difficult to achieve the desired performance and processing speed.

In the method (3), although the performance processing speed can be varied, a certain idle time is provided in the advance control section for each instruction between consecutive instructions.

Although the time in the advance control section does not change, the time for performing arithmetic processing differs depending on the content of instruction execution. For this reason, there are many instructions (such as SS instructions) that take longer to process than the preceding control part of the instruction.

It is difficult to achieve a desired processing speed, and a similar drawback occurs when many instructions with short arithmetic processing speeds are generated.

[Purpose of the invention]

An object of the present invention is to provide a performance control method that allows desired performance to be set in an information processing device.

[Summary of the invention]

The present invention achieves its objectives by generating arithmetic processing speed in the arithmetic processing stage.

The present invention has a performance control means that responds to a calculation execution signal from the calculation control means that controls the calculation of the calculation unit, and provides the calculation control means with a signal instructing preset calculation processing, and executes the calculation. Controls signal generation, creates computational idle time, and controls performance.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

The first [1] indicates an arithmetic processing unit. The arithmetic processing section receives decoded instructions, operands (or operand addresses), etc. from a not-shown advance control section, and executes the instructed arithmetic operations. The arithmetic processing section.

Performance control circuit 2, arithmetic control circuit 3. It includes a calculation unit 4.

FIG. 2 shows details of the performance control circuit 2. Performance control circuit 2
are 21 to 24 latches, 25 to 28 NOR gates,
It consists of a 29.30 AND gate and 2A, 2B terminator connectors. The output FWAIT signal from the performance control circuit 2 represents an arithmetic idle processing time command signal and is connected to the arithmetic control circuit 3.

FIG. 3 is a diagram showing how performance can be controlled by the performance control circuit 2. The inputs of NOR gates 26 and 27 are always at low (L) level, so the outputs are always at high (L) level.
H) level. Performance can be changed by connecting terminator connectors 2A and 2B to the outputs of the NOR gates 26 and 27. In the figure, the Q mark indicates that the terminator is installed, and the - mark indicates that the terminator is not installed. Terminator connector 2A
.

Each model is set so that when both of 2B are installed, model 1 has the highest processing capacity, and when both are not installed, model 3 has the lowest processing capacity.

FIG. 4 shows the arithmetic control circuit 3 and the arithmetic unit 4. 31
-33 are latches, 34-36 are NOR gates, and 37 is a register C3DR138 is a decoder. register 3
7 is a register that holds microinstructions read from control memory C5 (not shown). When the latch 32 is set (E X B = "O"), the decoder 38 decodes the microinstruction in the register 37 and provides an arithmetic control signal to the arithmetic unit 4 to control the execution of arithmetic operations in the arithmetic unit 4 .

FIG. 5 shows an instruction operation cycle diagram of model I.

5 is a machine cycle, white circle 6 is an operation cycle that is not the end cycle of an instruction (hereinafter referred to as EOP cycle), and hatched circle 7 is an EOP cycle. It shows how numbers 1 to 6 are calculated. For example, the first instruction completes its operation in two cycles, and thereafter the instructions are executed without empty cycles. Figure 5 shows that the time (number of cycles) required for each instruction's operation is different. .

Figure 6 shows the arithmetic control time chart of model 1. Figure 2 shows that both terminator connectors 2A and 2B are installed, so the CNCTA and CNCTB signals go to "H" level, inhibiting the NOR gate 28. . That's why F
The WAIT signal is always at L level (0'').

FIG. 7 shows an instruction operation cycle diagram of model 3.

φ8 represents an operation empty cycle in which no operation is executed.

FIG. 8 shows an arithmetic control time chart of Model 3.

This figure is in sync with Figure 7.

An example of its operation will be explained below.

First of all, the arithmetic control latch EXA31 in the arithmetic control circuit 3 shown in FIG.
is set and holds the value until a stop signal is received. When the latch EXA31 is set, if the inhibit signal FWAIT from FIG. 2 is not II I II, the latch EXB32 becomes ``1'' after half a cycle, and the latch EXC33 is set after the half cycle. The arithmetic unit 4 performs arithmetic processing based on the arithmetic control signal obtained by decoding the microinstruction output register 37 by the decoder 38. When the FWAIT signal becomes 1”, the latch EX
B32 becomes "0", and as a result, the arithmetic control signal is suppressed and the arithmetic processing performed by the arithmetic unit 4 is also stopped. This state is represented by a calculation empty cycle φ8.

The fifth case is where the calculation process is executed sequentially without being stopped.
It will look like Model 1 in Figure 6.

Next, a case in which calculation is stopped will be described using Model 3 as an example. Model 3 does not have terminator connectors 2A and 2B installed, so the CNCTA/CNCT shown in Figure 2
The B signal is always "L'".

The AND result of NOR gate 28 is reflected in FWAIT. The latches 21 to 24 in the performance control circuit 2 are initially 110
Initialized to #l. Also, since the CNCTB signal is always at #L II level, the AND gate 30
The output will always be 1101+. Output WA of latch 22
Since IT2L is also 'O', the NOR gate 25 output is #
I become II. Therefore, as shown in the arithmetic processing cycle diagram of FIG. 8, when EXB outputs one cycle, the output WA I T 2 R of the latch 21 is set to l''. This output is ANDed with EXC by the NOR gate 28, and the FWA
It becomes an IT signal. When the FWA IT double signal becomes ``1'',
In order to inhibit latch EXB32 in Fig. 4, latch E
XB 32 is set to 110 TT. After half a cycle, it is transmitted to latch EXC33, and as a result, FWAIT
The signal becomes “0” for one cycle (FWAIT release)
,.

When FWAIT is released, 111 of latch EXA31
#l The contents are transmitted to the latch EXB32, and as shown in the arithmetic control time chart in Figure 8, when EXB32 goes out for two cycles, F-take AIT goes out for one cycle, which is repeated, resulting in a cycle where EXB is "1". The cycle in which FWAIT is 1'' is a calculation idle time.

Model 2, which only implements terminator 2B, will not be described in detail, but the main point is WAIT latch 21゜22.23
．． When the operation execution signal EXB is output for 3 cycles by the combination of 24, the operation that FWAIT is output for 1 cycle is repeated.

In this example, we have described an example in which a constant total calculation processing time is generated for a constant calculation processing time, but by slightly changing the update conditions of the performance control circuit, it is also possible to generate the following calculation idle time. .

1. Generate idle processing time only after the first arithmetic processing cycle for each instruction.

2. Generate idle processing time only for specific instructions.

It is also possible.

In this embodiment, the calculation processing time of the information processing device can be changed to a predetermined calculation processing time.

It becomes possible to create multiple models of information processing devices with different performance differences from one information processing device. In addition, the processing capacity can be transferred simply by changing the combination of control signals, which has the effect of being simple and quick.

〔Effect of the invention〕

According to the present invention, since idle time is generated during calculation execution, performance matching the set performance can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Figure 2 is a block diagram showing details of the performance control circuit in Figure 1, Figure 3 is a diagram showing the relationship between terminator/connector implementation and performance, and Figure 4 is a block diagram of the arithmetic control circuit and arithmetic unit in Figure 1. Figure 5 is a diagram showing the instruction operation cycle of model 1, Figure 6 is an operation control time chart of model 1, Figure 7 is a diagram showing the instruction operation cycle of model 3, and Figure 8 is a diagram showing the instruction operation cycle of model 3. 3 is an arithmetic control time chart. 2... Performance control circuit, 3... Arithmetic control circuit. 4...Arithmetic unit. Figure 5 Figure 6 ζ

Claims (1)

[Claims] (1) It has a performance control means that responds to a calculation execution signal from the calculation control means that performs calculation control of the calculation unit, and provides a signal instructing a preset calculation process to the calculation control means, and controls the calculation execution signal. A performance control method for an information processing device characterized by controlling generation.