JPS6188340A - Information processor - Google Patents

Abstract

PURPOSE:To improve the throughput of a system by constituting that an output token reaches directly an output controller as the result from an operation processing means to eliminate an overhead for output. CONSTITUTION:When an inputted token is an input not requiring processing, an input control section 1 transfers it to an output control section 8 directly and when the input requires processing, the token is transmitted to a link table section 2. In this case, operation control information in response to the destination address is added to the token from the control section 1 or the operation processing section 6 and the destination address is revised to arrange the token inputted by a waiting memory section 4 via a function table section 3. Then the token via a cue section 5 is subject to operation by the processing section 6, the destination address is transmitted to the table section 2 in response to branch information to form a link or transmit it to an output control section 8 via an output cue section 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus that performs pipeline processing based on a data flow method.

[Conventional technology]

Regarding conventional information processing devices of this type, there is a data flow type processor LSIJ aimed at the image processing field.
Matsumoto Ka2-Ukei Electronics, N1340.

pp, 181-218.1984.4.9. ) The paper has been published. Hereinafter, a conventional example will be explained based on this paper.

FIG. 4 shows a conventional information processing device of this kind. In the figure, 1 is an input control section, 8 is an output control section, 2 is a link table section, 3 is a function table section, 4 is a waiting memory section, and 5 is a 6 is an arithmetic unit, and 7 is an output queue part.

In addition, FIG. 5 shows the transition of token formants and the contents of each table in the device of FIG. The number, 102 is the destination address, 103 is the data, and in Token II, 1)
2 is the next destination address, 105 is the function table address, and 106 is the selection code. Also l
--In token 12, 107 is the waiting memory address, 108 is the opcode, and in token 13, 1
31.132 is data 1. This is data 2.

Further, in (f) to (h) of the same figure, 14 to 16 are a link table, a function table, and a waiting memory, and 0 to 127.0 to 63.0 to 51) indicate their addresses, respectively. In addition, in the link table 14, 205 is a function table address, 212 is a next destination address, 206 is a selection code,
In the function table 15, 207 is a waiting memory address, and 208 is an operation code. Also, in the waiting memory 16, 230 is data.

Next, the operation will be explained.

For the information processing apparatus configured as shown in FIG.
Token 9 shown in Figure (a) is input. Input side fa1
) Module number MN10 of token 9 that arrived at part 1
1 is compared with the module number given to this information processing device in advance, and if they do not match, this token is sent as is to the output control unit 8 and output to the outside, and only if they match, the module number MNIOI is removed. The token 10 (see FIG. 3(b)) is sent to the link table section 2.

In the link table section 2, the destination address I of the token 10 is
The link table LT14 with D102 as the address
Refer to the function table address FTA 205 for reading the function table FT15.
．． Next destination address I for reading the link table when this token arrives at the link table unit 2
D'212 and the selection code 5EL206 representing the classification of commands to be performed on this token are read out and added to token 10 to create a new token 1) (
(see (C) in the same figure) and sends it to the function table unit 3.

The function table section 3 refers to the function table FT15 using the function table address FTA105 as an address, and obtains a parameter group that determines the processing content in the subsequent pipeline stage. Some of the obtained parameters remain as token 1)
However, other parts are reprocessed by a control section (not shown), and the result is added to token 1) to form a new token 12, which is sent to the waiting memory section 4.

For example, if the token 1) received by the function table section 3 is a token that becomes one operand of a two-operand operation, and the token that should become the other operand has already arrived and is waiting in the waiting memory section 4. Then, in the function table section 3, this token 1) is an operation code 0PC20B representing the type of operation.
and the memory address DMA2 of the waiting memory DM16 where the other operands of the two-operand operation are stored.
07 and is added to token 1) to form token 12 (see dl in the same figure).

The waiting memory unit 4 reads data 230 corresponding to other operands necessary for execution of the operation and stores the token 13 (see figure (el)) having two operands 131 and 132.
(see) to the queue section 5.

The queue section 5 is composed of a first-in/first-array 1-memory, and when this token 13 reaches the head of the first-in/first-out memory, it is sent to the arithmetic section 6 and arithmetic processing is executed. The calculation result token has the format shown in FIG. 5(b), and this token 10
is sent to the link table section 2.

In this way, the input token is stored in the link table section 2. Funk thin table section 3. Waiting memory section 4. Part 5. Necessary processing is performed by going around the pipeline ring 50 consisting of the arithmetic unit 6 several times, and then it passes through the link table unit 2 again to the function table unit 3 for output, where it is output again. The command is received, sent to the output queue section 7 via the waiting memory section 4 and the queue section 5, and further outputted to the outside via the output control section 8.

As is clear from the above explanation, when a token is input to a conventional information processing device, it generally cycles through the pipeline ring n times for arithmetic processing, and finally vibrates again to output it to the outside. It will go around the line ring (excluding the calculation section).

Therefore, in the case of an input token that requires only one operation, even though the processing would normally be completed after going through the pipeline ring once, it has to go through the pipeline ring again for output. Must be.

In other words, the overhead for output is the same as the original processing time. In order to relatively reduce this overhead, it is conceivable to increase the number of arithmetic operations performed within the same information processing device and increase the number of cycles n of pipeline rings for arithmetic operations. However, increasing the number of rounds means that the amount of processing for tokens input to the device increases, and the throughput of the device becomes approximately 1/n of the number of rounds.

[Problem to be Solved by the Invention 3] As explained above, in conventional information processing devices, if the number of times a single token in the same information processing device circulates through the pipeline ring increases, the system throughput deteriorates. On the other hand, in order to increase system throughput, if processing is distributed among a large number of 1n information processing devices and the number of cycles through the pipeline ring of each information processing device is reduced, overhead due to output becomes apparent. In the worst case, the resource utilization efficiency is almost 1.
/2.

The present invention has been made with the aim of solving the latter of the above problems, that is, providing an information processing device with high system throughput (and high resource efficiency) by eliminating the overhead for output. .

Means for Solving Problem C] In order to solve the above problems, in the present invention, branch information is newly added to the information given to the token by the arithmetic instruction giving means, and the arithmetic processing means is added to the branch information. Accordingly, the token after the arithmetic processing was configured to be branched from the pipeline ring.

[Effect]

By taking the above measures, the result output from the arithmetic processing means can directly reach the output control means, so there is no need to go around pipeline rings for output processing, and overhead is removed, and an information processing device with high system throughput can be realized.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an information processing device according to an embodiment of the present invention,
FIG. 2 shows the format transition of the token and the contents of the table memory referenced by the token.

The device of this embodiment consists of the same blocks as the conventional one, but the tokens that have been processed are outputted from the arithmetic unit 6 to the queue part 7 instead of the queue part 5. The result destination code (branch information) 1) 9 for instructing branching in the arithmetic unit 6 is outputted to the outside via the output control unit 8, and the function table unit 3 outputs the result destination code (branch information) 9 to the token 1. ), the function table 150 also stores a result destination code 219.

FIG. 3 shows the internal configuration of the arithmetic unit 6, and in the figure,
61 is an arithmetic unit that performs an arithmetic operation on data 1.2 (131, 132) according to the operation code 108, and 62 is an arithmetic unit that performs an arithmetic operation on data 1.2 (131, 132) according to the operation code 108; Selector output to part 7, 63 is destination address 102 and module number 10
This is a latch that opens and closes 1.

Next, the operation will be explained.

For the information processing apparatus configured as shown in FIG.
Token 9 shown in Figure (a) is input. Input control section 1
The module number MN101 of the token 9 that has arrived is compared with the module number given to this information processing device in advance, and if there is a mismatch, the token is sent as is to the output control unit 8 and output to the outside, and if there is a match. Only in this case, the token 10 excluding the module number MN101 (see (b) in the same figure) is sent to the link table section 2.

In link table section 2, destination address r of token 10
The link table LT14 with D102 as the address
, the function table address (arithmetic control information) FTA 205 for reading the function table FT 150, the next destination address iD' 212 for reading the link table when this token arrives at the link table unit 2, and Selection code 5E indicating the classification of commands to be performed on this token
L206 and the like are read out and added to the token 10 to form a new token 1) (see (C) in the figure) and sent to the function table section 3.

The function table section 3 refers to the function table FT150 using the function table address FTA 105 as an address, and obtains a group of parameters that determine the processing contents in the subsequent pipeline stage. Some of the obtained parameters are added as they are to the token 1), but other parts are reprocessed by a control unit (not shown) and the results are added to the token to create a new token 120 ((d) in the figure). ) and is sent to the waiting memory section 4.

For example, the token 1) received by the function table section 3 is a token that becomes one operand of a two-operand operation, and the token that should become the other operand has already arrived and is waiting in the waiting memory section 4.
Moreover, assuming that this token is output to the outside after the arithmetic processing, this token 1) in the function table section 3 stores an operation code (operation instruction code) OPC208 indicating the type of operation and other operands of the two-operand operation. the waiting memory address DMA 107 of the waiting memory DM16, the result destination code (branch information) RDC 219 indicating that the destination of the token after the arithmetic processing is the output queue section 7, and this information processing device. The next module number MN'21) indicating the information processing device on which the token output from is to be processed next is obtained, and these are added to token 1) to form the token 120. In this case, the next destination address ID'212 added by the link table unit 2 indicates the address of the link table of the information processing device indicated by the next module number MN'21).

The waiting memory unit 4 reads data 230 corresponding to other operands necessary for execution of the operation and stores the token 130 (see figure (e)) having two operands 131 and 132.
1) to the queue section 5. The queue section 5 is composed of a first-in/first-out memory, and when this token 130 reaches the head of the first-in/first-out memory, it is sent to the arithmetic section 6 and arithmetic processing is performed. In the arithmetic unit 6, after the arithmetic unit 61 performs arithmetic processing according to the operation code 0PC108, the resulting destination code RDC1 in the token 130 is
The selector 62 sends the result token to the output queue part 7 or the link table part 2 according to the contents of 09. The format of the result token when sent to the output queue part 7 is the format shown in FIG. 2(a), and the format of the result token when sent to the link table part 2 is the format shown in FIG. 2(b). .

As is clear from the above description, according to the information processing apparatus according to the present invention, an input token that requires n arithmetic processing completes the desired processing by cycling through the pipeline ring n times, and is then sent to the outside. can be output to. On the other hand, in the conventional information processing device, it is necessary to travel around the pipeline ring (H+1) times because there is an over node for output.

This effect is particularly important when attempting to improve processing throughput by cascading a large number of pipeline information processing devices 100a to 100e and dividing the program into functions, as shown in FIG. When a single pipeline type information processing device is used, it is assumed that the pipeline ring is circulated m times for processing. If this is expanded to a system in which m pipeline type information processing devices are cascaded as shown in Fig. 6, according to the conventional example, each information processing device includes pipeline processing including output processing. The throughput is 1/(2tp) because the ring is visited twice, whereas in the case of the information processing apparatus according to the present invention, the throughput is 1/lp because each round is completed once. Here, tp is the time required for one stage of the pipeline.

In other words, for a system configuration that aims to obtain maximum throughput, it is approximately 1
The throughput improvement is close to 0.00%.

Note that in the above embodiment, the input control section and the output control section.

Although the example shown here has one block for each pipeline ring, the input control section and output control section, which have the slowest processing speed in this device, can be provided with multiple blocks each to further increase throughput. can be improved.

In addition, in the case of a device that has only one person and one output control unit, the multiprocessor can only be configured with a cascade connection as shown in Figure 6, but in the case of a device that has two people and two output control units, two-way communication is possible. It is possible to configure various networks such as FFT butterfly, shuffle net (a type of butterfly), and double loop, and it is possible to easily construct processor coupling topology.

〔Effect of the invention〕

As described above, according to the present invention, the result output from the arithmetic processing means is configured to be able to directly reach the output control means, so the overload for output is eliminated, and the system throughput is high and resource efficient. This has the effect of providing a good information processing device.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing the configuration of a pipeline type information processing device according to an embodiment of the present invention, and FIG.
(e) is a diagram showing the configuration of a table memory referred to in the pipelined information processing of FIG. 1, FIG. 3 is a diagram showing the internal configuration of the arithmetic unit of the device in FIG. 1, and FIG. 4 is a conventional example. FIGS. 5A to 5H are functional block diagrams showing the configuration of the pipeline information processing device of FIG. 6
The figure is a diagram showing a system configuration in which a large number of Vibrine type information processing apparatuses shown in FIG. 1 are connected in cascade to perform distributed processing. In the figure, 1 is an input control section (input control means), 2 is a link table section (destination address conversion means), 3 is a function table section (operation instruction provision means), 4 is a waiting memory section (waiting means), and 5 is a queue 6 is an arithmetic processing means, 7 is an output queue part, 8 is an output control section (output control means), and 5o is a pipeline ring. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In an information processing device that inputs and processes a token having data and a destination address for obtaining its arithmetic control information, it is determined whether the input token is an input that requires processing, and only the input that requires processing is described later. an input control means for inputting to the pipeline ring; an output control means for outputting non-processing input from the means or tokens from the pipeline ring described later; Destination address conversion means for adding arithmetic control information corresponding to the destination address to the token and updating the destination address; an arithmetic instruction for adding an arithmetic instruction code and branch information to the token from the means according to the arithmetic control information; A token queuing means for arranging the tokens inputted from the means, and an arithmetic processing means for performing arithmetic operations on the tokens from the means and outputting them to the destination address conversion means or the output control means according to the branch information. An information processing device comprising: a pipeline ring;