JPS58181168A - Autonomous processor array system - Google Patents

Abstract

PURPOSE:To operate processors in parallel by the distributed control, by connecting autonomously operating processors into an array by the data driving control and adding a tag to data and operating processors asynchronously. CONSTITUTION:While holding the sequentiality of the data sequence inputted from the same input terminal, plural autonomously operating processors 1 are connected into an array by a data controlling part. The processor 1 consists of a link memory part 2, an execution controlling part 3, and an operating part 4, and input terminals 15 and output terminals 16 are connected to the operating part 4. A first-in first-out queue is provided in the input side of each part of the processor 1, and respective parts are connected into a loop, and the data transfer is performed in the packet form. A tag is added to transfer data, and the selection of an operation in the processor 1 and the selection of an opportunity of the start of this operation, an opportunity of movement to another processor, and a movement destination are performed by the tag itself, and processors 1 are operated asynchronously, and thus, processors 1 are operated in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an autonomous processor array system, and more specifically, the present invention relates to an autonomous processor array system, and more specifically, a series of data series processes such as signal processing, matrix operation processing, and sorting are performed using a large number of LSI chip processors. The present invention relates to a computer system that gives autonomy to the operation of each processor when processing in a line, eliminates the need for centralized management, and enables operation under distributed control.

Conventionally, a large number of LSI chips are arranged and connected in a regular manner, and each processor performs calculations on a data stream manually input from time to time according to a predetermined procedure, and transfers the processing results to a predetermined neighboring processor. A computer method is known in which data is processed through several processors.

An example of the conventional configuration is shown in FIGS. 1 and 2.

FIG. 1 is an example in which real-time filter processing is realized by one-dimensionally combining nIIMI processors 1 having a product-sum calculation function y4-y+a+x. Also, Figure 2 shows the product-sum calculation function C+-
This is an example of combining processors with C10aγb into a hexagonal structure array to realize banded matrix operation C=A, x13. The methods shown in Figures 1 and 2 were proposed by H.T. Kung of Carnegie Mellon University in the United States (I-I
, T. Kung; Let's I). sign
Algorithms for VIJS I Sys
tems, CMU-C8-79-151, Car
negie-Mellon University,
1979).

However, in the conventional system, each processor must be executed synchronously using a single synchronization signal, and therefore only a fixed function can be realized. Therefore, each processor had to be specially designed to suit the calculation purpose of the entire array, resulting in a lack of flexibility.

The purpose of the present invention is to eliminate the drawbacks of the conventional technology as described in -1-.
An object of the present invention is to provide an autonomous processor array system that gives autonomy to each processor, asynchronously executes the execution of each processor, and enables parallel operation by distributed control of each processor.

To achieve the above object, the present invention combines processors that operate autonomously into an array using data-driven control, and tags data to control the selection and activation of operations within each processor. The data itself determines the trigger, the trigger for moving from one processor to another, and the selection of the destination processor, and each processor is thereby operated asynchronously, and data strings input manually are sequentially transferred in a pipeline manner. It is characterized by processing in series.

Below, the contents of the present invention will be explained in detail based on the illustrated embodiments.

FIG. 3 is an embodiment of the present invention, and shows the overall configuration of an autonomous processor array in which six autonomous processors 1 that operate on a data drive are connected adjacently. Here, each processor l has the configuration shown in FIG. In FIG. 4, 2 is a link memory section, 3 is an execution control section, and 4 is an arithmetic section, each section having a first-in, first-out (FIFO) queue on the input side.
connected in a circular manner. The calculation unit 4 is further provided with an input terminal 5 and an output terminal 6. Data transfer between these circularly connected parts is performed in packet format.

FIG. 5 shows the field structure of the packet. In FIG. 5, (a) shows the operand packet (link memory unit 2
- In the execution control unit 3), 7 is an instruction word address, 8 is a bit indicating the operand position, and 9 is operand data. (b) and (C) are instruction packets (execution control unit 3 - calculation unit 4), (b) is a one-operand type instruction bucket),
(C) is a two-operand type instruction packet. child\
10 is a bit indicating whether this packet is a 1-operand type or a 2-operand type, 11 is a Hatarei code, 12 is a link memory address, 13 is operand data, 14 is first operand data, and 15 is second operand data. It is. (d) is the result packet (calculation unit 4 - link memory 2
), 16 is a link memory address, and 17 is operand data.

(e) is the human output Bakut, and the field configuration is (d)
The result packet is the same as the result packet, 18 is the link memory address, and 19 is the operand data. (a)-(e)
In the field configuration, 12, 16, and 18 serve as tags attached to data, and 7 indicates the address of the instruction memory in the execution control unit.

FIG. 6 shows an example of the configuration of the execution control section 3 in FIG. 4.

20 is fi'IF'o queue, 21 is instruction memory, 22
2 is a data memory, 23 is a decoder, 24 is a data memory control circuit, and 25 is an instruction code synthesis circuit.

The data memory 22 functions both as a memory for research addresses and as an associative memory for content access. FIG. 7 shows the field configuration of instruction words stored in the instruction memory 21. 26, 27, :30 are respectively 10 in Figure 5.
, 11 and 12. Two bits distinguish whether the first operand is a constant or not, and two bits distinguish whether the second operand is a constant or not. FIG. 8 shows the field configuration of the memory cells of the data memory 22. 31
is a bit indicating whether or not this memory cell is in use.

32, 33.34 are the same as 7.8.9 in FIG. 5, respectively. 1 (the e7 section consists of a bit 31 indicating whether this memory cell is in use or not and a command address 32,
Used as a key during associative access.

FIG. 9 shows an example of the configuration of the arithmetic unit 4 in FIG. 4. 35
is a FIFO queue, 36 is an arithmetic unit, 37 is an output terminal control circuit, 38 is an input terminal control circuit, 39 is an arithmetic unit selection circuit, and 40 is an arithmetic unit output circuit.

FIG. 10 shows an example of the configuration of the link memory section 2 in FIG. 4. 41 is a FIFO queue, 42 is a link memory control circuit, and 43 is a link memory (linear address).

FIG. 11 shows the field configuration of the memory cells of the link memory 43. 44 and 45 are the same as 7 and 8 in FIG. 5, respectively. 46 is a bit indicating whether or not the following memory cell is related to the packet currently being processed.

To realize Kuog's idea in a data-driven manner, processing of data series is essential. This method is a processing method characterized by preserving the order of data series. The operation of this autonomous processor array will be explained below.

FIG. 12 shows how instruction word addresses are stored in the link memory in association with a data flow graph. In Figure 12, (a) is the link memo IJ, (
b) The diagram is a data flow graph. The result of the multiplication is sent to three actors (addition, division, subtraction). Correspondingly, the link memory stores the command address and operand position of each actor (the numerical value H multiplied by the actor's human power). Now, assuming that the result packet has the result of multiplication, the link memory address 16 points to the first address of the series of memory addresses. 1st
In the example of FIG. 2, it refers to the memory address corresponding to the addition after. Bit 46, which indicates whether a subsequent memory cell is associated with the packet currently being processed, has a value of °°0'', indicating that the next memory address is also associated with this packet, and a value of 1'''. indicates that the next memory address is unrelated to this packet.

The result packet is put into the queue 41 of the link memory unit 2. Link memory control circuit 42 queues packets 4
1, read out the link memory 43 using the link memory address 16, form an operand packet, and send it to the execution control unit 3. Furthermore, check bit 46, and if the value is "o", read the next address,
It composes an operand packet and sends it to the execution control unit 3. This operation continues until the value of bit 46 becomes 1''.

The execution control unit 3 reads the packet from the queue and reads the instruction code 27 from the instruction memory 21 according to the instruction address 7 of the packet. When this instruction is a two-operand type instruction, the data memory 22 is accessed associatively by using the instruction word address 7 as ke.

As a result, the following cases occur.

(1) There are no operands with the same ke (one operand has not arrived).

(11) There is one or more operands that also have 6y. In addition, there are operands with different operand positions (arrival of both operands).

(iii) There is one or more operands with the same key. In addition, there are no operands with different operand positions (data series collision).

The execution control unit 3 operates as follows in each case.

In the case of (1): Store the arriving operand in the cell with the lowest address among the empty cells in the data memory 22.

In the case of (11), 1 is the same as that of the other operand, and the operand at the lowest data memory address is paired with the operand, a quality bucket is created and sent to the arithmetic unit 4. At this time, the data memory control circuit 24 checks the operand attribute bit in the instruction code, and if the operand is constant data, it holds it in the operand memory. If it is not constant data, release this memory cell T
Le.

In the case of 011): Operands having the same key and the same operand position are stored in the data memory 22 so that their arrival order matches the order in which they are stored in the data memory (address - ascending order).

If the packet taken out from the queue 20 is a one-operand type packet, an instruction code 27 is added and sent to the arithmetic unit 4.

The decoder 23 separates packets into one-operand type packets and two-operand type packets.

Also, instruction code synthesis cycle 11Il! +25 is for sending the instruction packet to the assembling operation section 4.

The calculation unit 4 operates as follows. If the instruction code is a transfer instruction to another processor, the packet taken out from the queue 35 is sent to the output terminal control circuit 37; otherwise, it is sent to the arithmetic unit 1 selection circuit 39. The output terminal control circuit 37 controls transfer to other processors. The arithmetic unit selection circuit 39 allocates packets to the arithmetic units 36. The layout method is on the circular image side that does not allow skipping.
It is 1. That is, the order in which the arithmetic units are allocated is determined in advance, and the arriving packets are allocated to the arithmetic units t1 in the order of arrival and in accordance with the allocation order. If the arithmetic unit that should be divided is in operation, the division waits until the completion of that 7-kable monument. Similarly, the arithmetic unit output circuit 40 performs cyclic fetch control that does not allow skipping. The arithmetic unit 36 performs arithmetic operations according to the instruction code.

By the above data memory control method in the execution control section 3 and the arithmetic unit allocation control and retrieval control method in the arithmetic section 4,
It is guaranteed that the data will not be overwritten in the data series.

FIG. 13 shows an example of processing performed by the present autonomous processor array, in particular an example of multiplication by an imperial matrix. FIG. 13(a) shows the data transfer relationship between processors. FIG. 13(I)) is a program to be applied to a type A processor, and FIG. 13(C) is a program to be applied to a type PRO processor. For example, in the multiplication node in Figure 1:3(b), a
and C means that when data is received, they are multiplied and the result is output to the arrow to the addition node. Moreover, the mark "." represents a branch.

For example, data coming from a is sent to both the multiplication node and d. The "0" mark represents confluence.

The times represent the initial values, and data with the value ``0'''' is generated only once.In the TypPro processor program, a terminal with no output designation (for example, the a and f) are removed from FIG. 13(C).

All data series input to the same terminal on a program are given the same link memory address, and data series input from different input terminals are given different addresses. Further, a data series requiring different processing is given an address different from any of the above. Therefore, one autonomous processor array can execute counting programs in parallel.

As explained above, in the processor array system of the present invention, each processor is data-driven and performs asynchronous and pipeline processing while maintaining the order of manually input data series, so there is no need to synchronously control each processor. Can be operated in parallel.

Furthermore, since the functionality of each processor is provided by a dataflow program, autonomous processors are
It can be designed and manufactured as an I-chip. Furthermore, since this autonomous processor array can process many data flow programs on a single unit, it can be operated as a general-purpose system. Furthermore, since the data of each program is distinguished by the link memory address, multiple processing can be performed.

[Brief explanation of drawings]

1 and 2 are diagrams showing an example of the conventional method, FIG. 3 is an overall configuration diagram of an embodiment of the method of the present invention, FIG. 4 is a configuration diagram of the processor 1 in FIG. 3, and FIG. FIG. 4 is a field configuration diagram of a packet transferred between each unit; FIG. 6 is a specific configuration diagram of the execution control unit 3 in FIG. 4; FIG. 7 is a field configuration diagram of the instruction memory 21 in FIG. 6; 8 is a field configuration diagram of the data memory 22 in FIG. 6, FIG. 9 is a specific configuration diagram of the arithmetic unit 4 in FIG. 4, and FIG. 10 is a specific configuration diagram of the link memory unit 2 in FIG. 4. FIG. 11 is a field configuration diagram of the link memory 43 in FIG. 10, FIG. 12 is a diagram showing the relationship between actors of the data flow graph and their storage addresses in the link memory, and FIG. 13 is a diagram of the present autonomous processor array. FIG. 3 is a diagram showing a processing example. ■... Processor, 2... Link memory section, 3... Execution details, 4. Arithmetic section, 5... Input terminal, 6...
Output terminal. Agent Patent Attorney Makoto SuzukiFigure 10Figure 12

Claims (1)

[Claims] (1) While maintaining the order of the data series input from the same input terminal, multiple processors that operate autonomously through data-driven control are connected in an array, and data is tagged and stored within each processor. The data itself determines the selection of an operation and the trigger for starting that operation, the trigger for moving from one processor to another, and the selection of the destination processor. An autonomous processor array system whose characteristic is to process data strings one after another in a pipeline-like chronological order.