JPH03113635A - Micro processor - Google Patents

Abstract

PURPOSE:To suppress the deterioration of execution efficiency by selecting either of an output from a shift means or an output from an incrementer based on control from an instruction decoder and outputting it to a program counter register. CONSTITUTION:When a branching condition shifting the output to the left by three bits by a shifter 2 is decoded in the instruction decoder 1, a branching address 9 which is shifted to the left by three bits is outputted from the shifter 2 and a multiplexer 3 selects the output of the shifter 2, whereby the output is inputted to a PC register 4. When a branching condition except for the condition is decoded from the instruction decoder 1, a value inputted to the shifter 2 is zero bit-shifted and is outputted to the multiplexer 3. When the decoded branching condition is realized, the instruction decoder 1 causes the multiplexer 3 to select the output of the shifter 2, and to input it to the PC register 4. When it is not realized, the instruction decoder 1 causes the multiplexer 3 to select the output of the incrementer 5 and to input it to the PC register 4. Thus, the deterioration of execution efficiency is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and more particularly to a microprocessor that has a fixed-length instruction system and implements a branch instruction when expanding an instruction space.

[Conventional technology]

With the recent development of LS/Lg manufacturing technology, microprocessors with high processing power have become available at low cost, and the operating frequency of such microprocessors has been increasing year by year, and the hardware has become highly integrated. ing.

In particular, in recent years, Microb [Gosekusa] uses a fixed-word instruction system to improve performance in order to reduce the burden on the decoder.A single word-fixed-length instruction consists of multiple sub-instructions, and the same LSI Simultaneous operation of multiple pieces of integrated hardware can be specified.

For example, one word fixed-length instruction is divided into a plurality of sub-instructions, and ALU operations, data transfer instructions, and other microprocessor internal controls are all performed simultaneously. Other instructions include branch instructions and immediate value load instructions. Each of these instructions holds a branch address part and an immediate data part as operands. Therefore, these branch instructions and immediate value load instructions can only be executed simultaneously with limited sub-instructions having short bit lengths.

That is, this is because the bit length of one instruction is limited.

[Problem to be solved by the invention]

As the conventional microprocessor described above becomes more complex in its application, the program tends to become larger and the branch distance tends to become larger. If the branch destinations are far apart, the bit width may not fit within the bit width of one instruction. Conventionally, such a bit width problem has been dealt with by using an interrupt vector or by using an instruction whose length is twice the unit instruction length.

However, in the former case, a vector area is required, and it may be necessary to initialize the vector area in advance. Furthermore, in the latter case, there is a problem that the execution efficiency is reduced because the length of the instruction is long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that does not require such an interrupt vector area, and can minimize the decrease in execution efficiency when branching by avoiding multiple instruction lengths.

[Means to solve the problem]

The microprocessor of the present invention includes an instruction decoder, a shift means for shifting an output from the instruction decoder by a predetermined amount, a program counter register, an incrementer for incrementing the value of the program counter register, and and a multiplexer for selecting either the output from the means or the output from the incrementer based on control from the instruction decoder and outputting the selected one to the program counter register.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes a shifter 2 that shifts the output from an instruction decoder 1 by a predetermined amount (including zero) based on a control line 6, and a program counter register (hereinafter referred to as P
C register) 4, a PC incrementer 5 that increments the value of the PC register 4, and either the output of the shifter 2 or the output from the PC incrementer 5 is incremented based on the control line 7 from the instruction decoder 1. The multiplexer 3 selects and outputs the selected data to the PC register 4.

FIG. 2 is an instruction format diagram of a conditional branch instruction of the microprocessor shown in FIG.

As shown in FIG. 2, this instruction format is formed from a branch instruction 8 of 4 bits, a branch address 9 of 13 bits, a branch condition 10 of 5 bits, and a transfer specification 11 of 10 bits. ing.

Let us now consider the case where the instruction space of a microprocessor whose instruction format holds only 13 bits as a branch address is expanded from 8 words to 64 words. Note that the shifter 2 changes the branch address from the instruction decoder 1 to 3 based on the control line 6 from the instruction decoder 1.
It is a shift circuit that shifts left by bits or O bits, and multiplexer 3 is the output from shifter 2,
It has a function of selecting one of the outputs from the PC incrementer 5 based on the control line 7 from the instruction decoder 1 and outputting it to the PC register 4.

First, one of the combinations of branch conditions 8 is assigned as a condition for shifting 3 bits to the left in shifter 2.

Next, when the instruction decoder 1 decodes the branch condition for shifting 3 bits to the left by shift j12, the control line 6 causes the shifter 2 to output a branch address 9 shifted to the left by 3 bits. Thereafter, the output of the shifter 2 is selected by the control line 7 and the multiplexer 3 and is input to the PC register 4.

On the other hand, when a branch condition other than the condition for shifting 3 bits to the left by shifter 2 is decoded from instruction decoder 1, the value input to register 2 via control line 6 is shifted by 0 bits and then output to multiplexer 3. . If this decoded branch condition is satisfied, the instruction decoder 1 uses the control line 7 to cause the multiplexer 3 to select the output of the shifter 2 and input it to the PC register 4. If the decoded branch condition is not satisfied, the instruction decoder 1 uses the control line 7 to cause the multiplexer 3 to select the output of the PC incrementer 5 and input it to the PC register 4.

FIG. 3 is a block diagram of a microprocessor showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment also uses a branch address in the instruction format to change the instruction space of a microprocessor that holds only 13 bits as shown in FIG. 2 from 8 words to 64 words or Consider the case of expanding to 128 words.

First, this embodiment is the same as the first embodiment described above except that a register 12 for holding the shift amount by the shifter 2 is provided. That is, the shifter 2 shifts the branch address 9 (see FIG. 2) from the instruction decoder 1 to the left by the value of the register 12 or by 0 bits based on the control line 6 from the instruction decoder 1. Further, the multiplexer 3 selects either the output from the shifter 2 or the output from the PC incrementer 5 based on the control edge 7 from the instruction decoder 1 and outputs it to the program counter 4.

Next, in this embodiment, one of the combinations of branch conditions 10 shown in FIG. 2 is assigned as a condition for shifting the value of the register 12 to the left in the shifter 2. For example, register 12 has 3
Set. As a result, the amount of shift when shifter 2 shifts to the left becomes 3 bits. Therefore, in the instruction decoder 1, when the shifter 2 decodes a branch condition that shifts the branch address by 3 bits to the left, the shifter 2 shifts the branch address by 3 bits to the left, and then outputs a signal from the control line 6. Thereafter, the multiplexer 3 selects the output of the shifter 2 according to a signal from the control line 7 and inputs it to the PC register 4.

Here, in the instruction decoder 1, when a branch condition other than the condition in which the shifter 2 shifts to the left by 3 bits is decoded, after shifting the value input to the shifter 2 by 0 bits,
The signal from the control line 6 is output to the multiplexer 3. If this decoded branch condition is satisfied, the instruction decoder 1 causes the multiplexer 3 to select the output of the shifter 2 using the control line 7, and inputs the selected output to the PC register 4. On the other hand, if the decoded branch condition is not satisfied, the instruction decoder 1 uses the control line 7 to cause the multiplexer 3 to select the output of the PC incrementer 5, and inputs the selected output to the PC register 4.

Note that by changing the value set in the register 12 from 3 to 4, the instruction space can be expanded to 128 words.

[Effects of the Invention] As explained above, the microprocessor of the present invention can expand the instruction space without changing the conventional instruction format or having multiple instruction lengths, without reducing execution efficiency. This has the effect of making it possible to achieve the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the present invention, FIG. 2 is an instruction format diagram of a conditional branch instruction of the microprocessor shown in FIG. 1 is a block diagram of a microprocessor showing an embodiment. FIG. 1... Instruction decoder, 2... Shifter, 3... Multiplexer, 4... Program counter register (
PC register), 5...PC incrementer, 6, 7
...Control line, 12...Shift amount holding register.

Claims (1)

[Claims] an instruction decoder, a shift means for shifting an output from the instruction decoder by a predetermined amount, a program counter register, an incrementer for incrementing the value of the program counter register, and an output from the shift means and from the incrementer. a multiplexer that selects one of the outputs of the program counter register based on control from the instruction decoder and outputs the selected output to the program counter register.