JPH02148134A - Arithmetic logic circuit - Google Patents

Abstract

PURPOSE:To miniaturize an arithmetic logic circuit by providing a priority level giving circuit with the function of a part of an overflow detecting circuit besides the essential function. CONSTITUTION:An overflow detecting circuit consists of exclusive OR circuits 2-0 to 2-31, a selecting circuit 3, a priority level giving circuit 4 (priority encoder PE), and a comparing circuit 5. The overflow detecting circuit in the arithmetic logic circuit having the priority level giving circuit 4 has the constitution using the circuit 4. That is, the priority level giving circuit 4 is provided with the function of a part of the overflow detecting circuit besides the essential function. Thus, the circuit area of the overflow detecting circuit is reduced to obtain the miniaturized arithmetic logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic logic circuit in a microprocessor, and particularly to a circuit for detecting overflow of a shift register thereof.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional arithmetic logic circuit. In the figure, SFT is a shifter, GR is a shift register, and ALtJ is a data processing execution unit (Arithmet
IC and Logic Unit), 5OVF
is an overflow detection circuit that detects overflow of the shift register, PR is a priority circuit (priority encoder) that detects the position of the most significant bit of the shift register, CTR is a control circuit, DBI is the first data path, and DB2 is the first data path. There are two data buses.

FIG. 3 is an explanatory diagram showing the detection principle of the overflow detection circuit SO■F of FIG. 2, and FIG. 4 is a block diagram of an actual overflow detection circuit constructed based on the detection principle of FIG. 3.

As shown in FIG. 3, the overflow detection circuit 5OVF operates at the most significant bit position MSB (
In the figure, the data at the 31st bit position) and each data at the other bit positions (30th to 0th bit positions) are exclusive-ORed, and then all the logicals of the results of these exclusive ORs are The sum is calculated, and if the result is a low level (hereinafter referred to as L), it is determined that the shift register is in an overflow state.

The actual overflow detection circuit is as shown in Figure 4.
In addition to the exclusive OR circuits EXORO to EXOR30 and the OR circuit ORI, the AND circuits ANDO to A N D 30
and a mask pattern generator MPG. This mask pattern generator M
As shown in the truth table in Figure 5, the PG converts 5-bit data into 31-bit data and outputs this 31-bit data to the AND circuits ANDO to AND30, and sets the overflow value. It is for the purpose of The AND circuits ANDO to AND30 are exclusive OR circuits HEX
The outputs of ORO to EXOR30 are ANDed with the output of the mask pattern generator MPG, and the result of this operation is output to the OR circuit ORI. Here, the logical sum of all the logical product values is taken, and if this logical sum is at a low level (hereinafter referred to as L), it is determined that the shift register is in an overflow state.

Furthermore, the priority circuit PE detects how many digits H from MSB the most significant bit of the shift register GR is in, and outputs a corresponding 5-bit signal as shown in the truth table of FIG. .

[Problem to be solved by the invention]

However, in the conventional example described above, the overflow detection circuit 5OVF must be provided independently from the priority injection positioning circuit PE, and there is a problem in that the circuit area becomes large when constructing the arithmetic logic circuit.

Therefore, the present invention has been made to solve the problems of the prior art as described above, and its purpose is to:
The object of the present invention is to reduce the circuit area of an overflow detection circuit and provide a more compact arithmetic logic circuit.

[Means to solve the problem]

The arithmetic logic circuit according to the present invention includes a shift register that stores a shifted value and shifts the shifted value; In an arithmetic logic circuit having a prioritized circuit for detecting an error, the to-be-shifted value at each bit position of the shift register is exclusive of the to-be-shifted value at the most significant bit position of the shift register. An exclusive OR circuit that calculates a logical sum receives the shifted value of the shift register and the output data of the exclusive OR circuit, and selectively assigns either the shifted value or the output data to the circuit with the priority. a selection circuit that outputs data from the exclusive OR circuit, a comparison circuit that compares the value detected by the circuit with a predetermined value when the selection circuit selects the output data from the exclusive OR circuit; and a control circuit that determines whether or not the shift register is overflowing based on the output of the shift register.

[For production]

In the present invention, when the selection circuit selects overflow detection, the exclusive OR circuit detects the target at the most significant bit position of the shift register (for example, the 31st bit position in a 0 to 31 bit shift register). The shift value and lower bit positions (for example, 0 to
Exclusive OR with the shifted value at the 30-bit position) is performed.

Then, in the prioritization, a circuit detects which digit from the most significant bit position the position of the most significant bit of the exclusive OR data (the position of the most significant 1 in the data) is located. The detected bit position of the most significant bit is compared with a predetermined value by a comparison circuit, and the control circuit determines whether or not the shift register is overflowing based on the comparison result of the comparison circuit.

In this way, the prioritization system uses an overflow detection circuit in an arithmetic logic circuit having a circuit, and the priority system uses the circuit. In other words, prioritizing the circuit
In addition to its original function, it is configured to function as a part of a circuit for detecting overflow, thereby saving the configuration for overflow detection.

[One example] The present invention will be explained below based on illustrated embodiments.

FIG. 1 is a block diagram showing the configuration of an arithmetic logic circuit according to the present invention. In this figure, the same components as in FIG. 2 are given the same reference numerals and will be explained.

This embodiment is a shift register overflow detection circuit 5O.
The overflow detection circuit 5OVF and the priority order are the same as those in FIG. 2 except that the circuit PE is integrated, so the explanation thereof will be omitted.
E (hereinafter, both will be referred to as overflow detection circuit 1) will be explained.

FIG. 7 is a block diagram showing the configuration of the overflow detection circuit 1 of this embodiment. As shown in the figure, the overflow detection circuit 1 includes exclusive OR circuits 2-0 to 2-31, a selection circuit 3, a priority II circuit 4, and a comparison circuit 5.
It is composed of

In addition, FIG. 8 shows the exclusive OR circuits 2-0 to 2-3 in FIG.
FIG. 9 is a circuit diagram showing the comparison circuit 5 of FIG. 7, and FIG. 10 is an explanatory diagram for explaining the operation of this embodiment.

The operation of this embodiment will be explained below based on FIGS. 7 to 10. First, the first line (signal 401) in FIG. 10 is 32-bit input data.

The most significant bit of this input data (#3 in Figure 8)
1) and others (shown in Figure 8 as #30 to #
0) are respectively input to exclusive OR circuits 2-0 to 2-30, where the respective exclusive ORs are calculated. Here, since the 31st bit of the signal 401 is 1, the output signals 500 to 531 of the exclusive OR circuits 2-0 to 2-30
is as shown in the second line of FIG.

The outputs of the exclusive OR circuits 2-0 to 2-30 (signals 500 to 531
) and input data (signal 401) are input, and the exclusive OR circuit 2- for shift overflow detection is input by the switching signal C sent from the control circuit CTR.
Either one of the output signals 0 to 2-30 or a prioritized signal for operation is selected, and the prioritized signal is output to the circuit 4.

To explain the case of detecting a shift overflow, the signals 500 to 531 on the second line in FIG. 10 are input to the priority circuit 4 as they are.

These signals 500 to 531 are prioritized as signal 601 and enter block 4a of circuit 4, where all bits (0 to 30 bits) except the 31st bit are set to 1 and are the most significant. The other numbers are set to 0 (signal 602 in FIG. 10).

This data is input to the next block 4b, which is the MS
The number of digits starting from B is detected and outputted as a 6-bit signal as PE output (signal 603 in FIG. 10).

This 6-bit PE output signal is accepted by the comparator circuit 5 only when shift overflow detection is selected by the selection circuit 3, and otherwise outputted from the data bus B in FIG. Signal 101 shown in FIG.
~105 indicates the above 6-bit PE output signal, and here, the 5-bit signal of the shifted values 201-205 and the PE output signals 201-206 are compared, and if the PE output signals 201-206 are large, In this case, the signal 301 becomes 1. The control circuit CTR receives the signal 301 and determines that the shift register has overflowed when the signal is 1.In this way, this embodiment combines the function of the mask pattern generator conventionally used as a configuration of the overflow detection circuit and the operation Focusing on the fact that the prioritization system provided in the logic circuit is similar in function to the circuit PE, the priority system uses the circuit PE as a part of the circuit for detecting overflow, and creates a mask pattern. Since a generator is not required, the circuit area can be saved compared to the conventional configuration, and the arithmetic logic circuit can be made smaller.

〔Effect of the invention〕

As explained above, according to the present invention, the overflow detection circuit in the arithmetic logic circuit having the circuit is configured to be configured using the circuit, and the prioritized configuration uses the circuit to perform the original function. In addition, since it also functions as part of the circuit for detecting overflow, the circuit area can be saved compared to conventional configurations that use mask pattern generators, etc., and thus the arithmetic logic circuit can be made smaller. It has the effect of being able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an arithmetic logic circuit according to the present invention, FIG. 2 is a block diagram showing an example of a conventional arithmetic logic circuit, and FIG. 3 is a detection principle of the overflow detection circuit shown in FIG. 2. FIG. 4 is a block diagram of an actual overflow detection circuit constructed based on the detection principle shown in FIG. 3, FIG. 5 is a truth table of the mask pattern generator shown in FIG. 2, and FIG. The figure shows a truth table of the circuit with the priority order shown in Fig. 2, Fig. 7 is a block diagram showing the configuration of the overflow detection circuit 1 of this embodiment, and Fig. 8 shows the exclusive OR circuit of Fig. 7. FIG. 9 is a circuit diagram showing the comparison circuit of FIG. 7, and FIG. 10 is an explanatory diagram for explaining the operation of this embodiment. 1... Overflow detection circuit, 2-0 to 2-30... Exclusive OR circuit, 3... Selection circuit, 4... Priority circuit, 5... Comparison circuit, CTR...・Control circuit (control circuit). Circulation based on this weak version 2 1) In-circuit block 7
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Claims (1)

[Claims] A shift register that stores and shifts a value to be shifted; and a shift register that stores a value to be shifted and shifts the value; an arithmetic logic circuit having a prioritization circuit for detecting, performs an exclusive OR of the shifted value at each bit position of the shift register and the shifted value at the most significant bit position of the shift register; an exclusive OR circuit; and a selection circuit that receives the shifted value of the shift register and the output data of the exclusive OR circuit, and selectively outputs either the shifted value or the output data to the prioritization circuit. and a comparison circuit that compares the value detected by the prioritization circuit with a predetermined value when the selection circuit selects the output data from the exclusive OR circuit, and a comparison circuit that compares the value detected by the prioritization circuit with a predetermined value; An arithmetic logic circuit comprising: a control circuit that determines whether a shift register is overflowing.