JPS61153739A - Interrupting circuit of microprocessor - Google Patents

Abstract

PURPOSE:To inform plural interruption factors to a CPU by using one interruption line, and to realize a function which is equivalent to having plural interruption lines, by constituting a title circuit so that a kind of the interruption is encoded and informed to the CPU. CONSTITUTION:In plural interruption factors, in case when only an interruption factor signal 2 is inputted to an interruption generating circuit 10, and interruption discriminating signal 16 which passes through an encoder 18 is encoded as '1000', becomes '8', and sent to a peripheral port (PPI)9. On the other hand, the interruption factor signal 12 sets a flip-flop 7 through a multi-input NOR circuit 17, and interrupting signal 2 is sent to a CPU8. The CPU8 reads the interruption discriminating signal 16 which is inputted to the PPI9, through a line 6 in order to detect by which one of four interruption factors the interruption is executed, and since it is '8', the interruption factor signal 12 is discriminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt circuit for a microprocessor that performs interrupt processing.

[Conventional technology]

FIG. 2 is a block diagram showing the interrupt circuit of a conventional microprocessor. In the figure, 1 is an interrupt cause signal, 2 is an interrupt signal, 3 is an external reset signal, 4 is a reset signal,
5 is an interrupt response signal, 6 is a data and control path line, 7 is a flip-flop, 8 is a microprocessor (hereinafter abbreviated as CPU), 9 is a peripheral port (hereinafter abbreviated as PPI), 10 is an interrupt generation circuit , 1°1 is a NOR circuit.

The interrupt circuit of a conventional microprocessor is configured as described above, and assuming that the need to interrupt the CPU 8 occurs externally, the set terminal SK of the flip-flop 7 constituting the interrupt generation circuit 10 is input from the outside.
When the interrupt factor signal 1 arrives, the flip-flop T enters the set (get) state, and an interrupt signal 2 is issued to the CPU 8 from its output.

When the cpty 8 detects the interrupt signal 2, the CPU 8 outputs the data and control path line 6.
The signal is sent to PP19 via . Note that PPl9 above refers to a buffer with a bidirectional latch function that is connected to the CPUg by a pass line, and is a general-purpose IC.
It exists as a peripheral function of the CPU. P above
Pl9 sends the above-described signal from the CPU 8 as an interrupt response signal 5 through the NOR circuit 11, and further sends it as a reset signal 4 to the reset terminal R of the flip-flop T, thereby resetting the flip-flop 7 (Re5et
) state.

Note that the external reset signal 3 is a signal for setting the flip-flop 7 to a reset state in the initial state of this system.

[Problem that the invention seeks to solve]

The conventional microprocessor interrupt circuit as described above has a problem in that only one interrupt factor signal 1 can be secured. A general K CPU does not have many interrupts, but in the past, C
Since only one interrupt factor is accepted for each interrupt intake port of the PU 8, there is a problem that if there are multiple interrupt factors, only one can be used as an interrupt and the others cannot be interrupted.

The present invention has been made to solve this problem, and an object of the present invention is to obtain an interrupt circuit for a microprocessor that can issue a CPUK interrupt using one interrupt line even when there are multiple interrupt sources. do.

[Means for solving problems]

The microprocessor interrupt circuit according to the present invention performs an OR operation on a plurality of interrupt factors, and uses the interrupt factor signal to
One interrupt signal is generated by setting the lip 70 knob, a plurality of interrupt cause signals are encoded by an encoder, and a code for identifying the type of interrupt currently occurring is sent to CPUK.

[Effect]

In this invention, multiple interrupt factors are encoded using an encoder and sent to the CPU.
It is possible to detect which factor among the plurality of interrupt factors described above caused the sent interrupt signal.

〔Example〕

FIG. 1 is a block diagram of an interrupt circuit of a microprocessor showing an embodiment of the present invention, and 1 to 11 are exactly the same as those described in the above-mentioned conventional example. In FIG. 1, assuming that there are n interrupt generation factors, 12 is an interrupt factor signal 1, 13 is an interrupt factor signal 2, 14 is an interrupt factor signal n -1, and 15 is an interrupt factor signal n. In addition, 16 is a coded interrupt identification signal, 17 is a multi-input NOR circuit, and 18 is a CP that handles multiple interrupt factors with a small number of lines.
This is an encoder for encoding to inform U'8.

Assume that in the microprocessor interrupt circuit configured as described above, interrupt factor signal 1 (12) among a plurality of interrupt factors is input to the interrupt generation circuit 10.

Then, interrupt cause signal 1 (12) is MOB, interrupt cause signal! An explanation will be given taking as an example the case where 'J (15) is 1.81 and n = 4.

In this case, only interrupt cause signal 1 (12) exists,
Since there are no other interrupt cause signals, encoder 1
8, that is, the above interrupt factor signal 1
The interrupt identification signal 16 corresponding to (12) is "8" when expressed in binary.0 The interrupt identification signal 16 encoded by the encoder 18 described above is sent to the PP19. On the other hand, the above-mentioned interrupt factor signal 1 (12) is taken out as one signal, that is, interrupt factor signal 1, from the output of the multi-input NOR circuit 17, and is applied to the set terminal S of the flip-flop 7 to Set state. Then, from the output of the above 7 lip-flop 7,
Interrupt signal 2 is sent to CPU8. The CPU 8 detects the above-mentioned interrupt signal 2 from the above-mentioned 7 lip-flop 7 and knows that an interrupt has occurred, but in order to know which of the four interrupt factors caused the occurrence.

PPl9 via data and control path line 6
The CPU reads the interrupt identification signal 16 inputted to the interrupt factor signal 1 and finds that it is "8", which corresponds to the interrupt factor signal 1 (12)K described above. From this K, the above-mentioned CPU 8 recognizes that the above-mentioned interrupt is an interrupt caused by the interrupt cause signal 1 (12) K, and starts processing the interrupt.
The interrupt response signal 5 is sent to the interrupt generation circuit 1 through PPl9.
0 to the NOR circuit 11, and further sends the reset terminal RK reset signal 4 of the flip 7 block 7 from the output of the NOR circuit 11, thereby setting the flip 70 block T in the reset state.

In the above embodiment, the number of interrupt factors is four, but any number can be specified. Also, C
Although the description has been made with one interrupt intake port in the PU 8, it goes without saying that the present invention can also be applied to a CPUK having a plurality of interrupt intake ports.

〔Effect of the invention〕

As explained above, in the past, only one interrupt could be made to a CPUK that had only one interrupt, but in this invention, the type of interrupt is coded and notified to the CPU. In actual processing, it is equivalent to having multiple interrupts, and it has the effect of making it easier to build a system using a CPU.However, in terms of cost, it can be made cheaper by just making a few changes to the conventional circuit. There are effects that can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interrupt circuit of a microprocessor showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional interrupt circuit of a microprocessor. In the figure, 1 is an interrupt cause signal, 2 is an interrupt signal, and 5
is an interrupt response signal, 7 is a clip 70 knob, 8 is a microprocessor (CPU), 9 is a peripheral board) (P
PI), 12 to 15 are interrupt cause signals, 16 is an interrupt identification signal, 17 is a multi-input NOR circuit, and 18 is an encoder. Note that the same reference numerals in each figure indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation

Claims (1)

[Claims] In a microprocessor interrupt circuit that allows a CPU to be interrupted by one interrupt line even when a plurality of interrupt factor signals exist, an encoder for encoding the types of the plurality of interrupt factor signals; A multi-input NOR circuit that receives an interrupt factor signal and generates one interrupt factor signal; a flip-flop that is set to a set state by the one interrupt factor signal and generates an interrupt signal at its output; and a flip-flop that performs interrupt processing using the interrupt signal. An interrupt identification signal coded corresponding to the CPU to be executed and the plurality of interrupt cause signals from the encoder is input, and an interrupt response signal is output according to a command from the CPU to reset the flip-flop. and a peripheral port, and when the CPU is interrupted by the interrupt signal,
An interrupt circuit for a microprocessor, characterized in that the CPU reads the interrupt identification signal from the peripheral port and can detect which of the plurality of interrupt cause signals the interrupt is caused by.