JPS63120523A - Ring counter circuit - Google Patents
Ring counter circuitInfo
- Publication number
- JPS63120523A JPS63120523A JP61266175A JP26617586A JPS63120523A JP S63120523 A JPS63120523 A JP S63120523A JP 61266175 A JP61266175 A JP 61266175A JP 26617586 A JP26617586 A JP 26617586A JP S63120523 A JPS63120523 A JP S63120523A
- Authority
- JP
- Japan
- Prior art keywords
- state
- ring counter
- counter circuit
- abnormal operation
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims abstract description 25
- 238000001514 detection method Methods 0.000 claims description 10
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000010615 ring circuit Methods 0.000 abstract 1
- 230000007704 transition Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 12
- 238000011084 recovery Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
リングカウンタ回路において、所定個数のフリップフロ
ップの出力がそれぞれ定められた状態になっていること
を検出した時、異常動作検出手段よりの信号でリングカ
ウンタ回路をクリアして初期状態に戻して、速やかに正
常動作に復旧させる様にしたものである。[Detailed Description of the Invention] [Summary] In a ring counter circuit, when it is detected that the outputs of a predetermined number of flip-flops are in a predetermined state, the ring counter circuit is activated by a signal from an abnormal operation detection means. This clears the information and returns it to its initial state to quickly restore normal operation.
本発明はリングカウンタ回路の改良に関するものである
。The present invention relates to improvements in ring counter circuits.
リングカウンタ回路は例えば分周回路等に使用されるが
、雑音等の為に誤ったデータが入力した場合には正常動
作の状態遷移と異なる状態遷移に入ることがあるが、こ
の様な時には速やかに正常状態に復旧させることが必要
である。Ring counter circuits are used, for example, in frequency divider circuits, but if incorrect data is input due to noise etc., the ring counter circuit may enter a state transition that is different from the normal operation state transition, but in such a case, it should be immediately It is necessary to restore normal conditions.
第７図は従来例のブロック図、第８図は第７図のタイム
チャート、第９図は第７図の状態遷移図で、第９図ｆａ
ｔは正常動作の場合、第９図（ｂｌは異常動作の場合を
示す。以下、第８図、第９図を参照しながら第７図の動
作を説明する。Fig. 7 is a block diagram of the conventional example, Fig. 8 is a time chart of Fig. 7, Fig. 9 is a state transition diagram of Fig. 7, and Fig. 9 fa
t indicates normal operation, and FIG. 9 indicates abnormal operation. Hereinafter, the operation shown in FIG. 7 will be explained with reference to FIGS. 8 and 9.
先ず、第８図−〇に示すクリアによって第７図に示す様
にリング状に接続されたフリップフロップ（以下、 Ｆ
Ｆと省略する）１〜３の端子Ｑが０゜ＦＦ４の端子０が
１ （端子ＯはＯ）になっているとする（第９図（８）
の００００の状態）。First, the flip-flops (hereinafter referred to as F
Suppose that the terminals Q of 1 to 3 (abbreviated as F) are 0 degrees, and the terminal 0 of FF4 is 1 (terminal O is O) (Fig. 9 (8)
0000 state).
この状態はクロックが加えられるとＦＦ４の端子０の１
がＦＦＩの端子りに加えられるので、リングカウンタ回
路は１ビツトシフトしてＦＦＩの端子０は１．ＦＰ２〜
４の端子Ｑは０になり第９図（ａｌの１０００の状態に
遷移する。In this state, when a clock is applied, the 1 of terminal 0 of FF4
is applied to the terminal of FFI, so the ring counter circuit shifts by 1 bit so that terminal 0 of FFI becomes 1. FP2～
Terminal Q of 4 becomes 0 and transitions to the state of 1000 in FIG. 9 (al).
そして、クロックが人力する度に第９図（８）に示す様
に１ビツトずつシフトして元の００００の状態に戻り、
又、これを操り返す。この時のＦＦＩ〜３の端子０及び
ＦＦ４の端子０の出力は第７図■〜■に示す様になる。Then, each time the clock is manually reset, it is shifted one bit at a time as shown in Figure 9 (8) and returns to the original state of 0000.
Again, manipulate this. At this time, the outputs of terminal 0 of FFI-3 and terminal 0 of FF4 are as shown in FIG.
次に、００００の初期状態の時に外部よりの雑音等によ
り誤ったデータが例えばＦＦ３の端子０から出力された
とすると第９図（ｂｌに示す様に、ＦＦＩ〜４の端子口
は００１０の状態になるが、この状態はクロックが入力
する度に１ビツトずつシフトし、第９図（ｂ）に示す様
に第９図（ａｌの正常動作時の状態遷移と異なる状Ｂ遷
移に入って復旧できなくなる。Next, if incorrect data is output from terminal 0 of FF3 due to external noise etc. at the initial state of 0000, the terminals of FFI to 4 will be in the state of 0010 as shown in Figure 9 (bl). However, this state shifts by one bit each time the clock is input, and as shown in FIG. 9(b), it enters a state B transition, which is different from the state transition during normal operation of (al), and cannot recover. It disappears.
そこで、第７図に示す様に異常動作検出の為のナンド回
路５を設けて５各ＦＰの端子０の出力が１になった。即
ち第９図（ｂｌの＊印の１１０１になった時にナンド回
路５から０が出力されてクリア信号が断になり、ＦＦＩ
〜４の端子ＣＬＲがＯになるので００００の状態に復帰
し、第９図（ａｌの状態遷移に入ることができる。尚、
ＦＦが４個の場合の異常動作の状態遷移は第９図（１）
）に示す１種類だけである。Therefore, as shown in FIG. 7, a NAND circuit 5 for detecting abnormal operation was provided so that the output of terminal 0 of each of the five FPs became 1. In other words, when it reaches 1101 marked * in Fig. 9 (bl), 0 is output from the NAND circuit 5, the clear signal is disconnected, and the FFI
Since the terminal CLR of ~4 becomes O, it returns to the state of 0000 and can enter the state transition of FIG. 9 (al).
The state transition of abnormal operation when there are four FFs is shown in Figure 9 (1).
There is only one type shown in ).
ここで、例えば正常動作０１１１の状態の時に雑音によ
って異常動作の状態遷移０１１０に入ったとすると１１
０１でしか異常動作が検出できないので復旧までの時間
は１ル一プ分の時間が必要であると云う問題点がある。Here, for example, if a state transition 0110 of abnormal operation is entered due to noise when the state is normal operation 0111, 11
There is a problem in that since an abnormal operation can only be detected at 01, the time required for recovery is one loop.
又、ＦＦＯ数が増加すると異常動作の状態遷移は１種類
だけではなく３種類、５種類と増加するので、それだけ
の数の異常動作検出回路を設けなければならないので回
路規模が大きくなると云う別の問題点もある。Furthermore, as the number of FFOs increases, the number of abnormal operation state transitions increases from one to three to five types, so that many abnormal operation detection circuits must be provided, resulting in another problem: the circuit size increases. There are also problems.
上記の問題点は第１図に示すリングカウンタ回路により
解決される。The above problems are solved by the ring counter circuit shown in FIG.
８はそれぞれ所定個数のフリップフロップの出力が定め
られた状態になっていることを検出した時、リングカウ
ンタ回路７をクリアする信号を送出する異常動作検出手
段である。Reference numeral 8 denotes an abnormal operation detection means that sends out a signal to clear the ring counter circuit 7 when it is detected that the outputs of a predetermined number of flip-flops are in a predetermined state.
本発明はリングカウンタ回路が異常動作をしている時は
、それぞれ所定個数のフリップフロップの出力が定めら
れた状態になるが、正常動作時にはこの様な状態になら
ないので、これを異常動作検出手段８で検出してリング
カウンタ回路をクリアすることにより復旧時間を短くす
ると共に３回路規模の拡大を改善した。In the present invention, when the ring counter circuit is operating abnormally, the outputs of a predetermined number of flip-flops are in a predetermined state, but since this does not occur during normal operation, this is detected by the abnormal operation detection means. By detecting at 8 and clearing the ring counter circuit, the recovery time was shortened and the expansion of the 3 circuit scale was improved.
第２図は本発明の実施例のブロック図、第３図は第２図
のタイムチャート、第４図は第２図の状態遷移図で、第
４図（ａｌは正常動作の場合、第４図ｔｂｌは異常動作
の場合を示す。尚、企図を通じて同一符号は同一対象物
を示す。又、排他的論理和回路８１．８２、ナンド回路
８３は異常動作検出手段８の構成部分を示す。以下、第
３図、第４図を参照しながら第２図の動作を説明する。2 is a block diagram of an embodiment of the present invention, FIG. 3 is a time chart of FIG. 2, and FIG. 4 is a state transition diagram of FIG. 2. Figure tbl shows the case of abnormal operation.The same reference numerals indicate the same objects throughout the plan.Also, exclusive OR circuits 81 and 82 and NAND circuit 83 indicate the components of the abnormal operation detection means 8.The following , 3 and 4, the operation shown in FIG. 2 will be explained.
先ず、第３図に示す様にリングカウンタ回路を構成する
ＦＦ ７１〜７４の端子０から第３図−■に示す様にク
ロックを８分周した出力が得られる（第３図−■〜■参
照）。そして、ＦＦ ７４の端子Ｑの出力がＰＦ ７１
の端子りに加えられるので、各ＦＦの端子０の状態は第
４図（ａ）に示す様に遷移する。First, as shown in FIG. 3, from terminals 0 of FFs 71 to 74 constituting the ring counter circuit, the output obtained by dividing the clock by eight as shown in FIG. 3-■ is obtained (FIG. 3-■ to reference). Then, the output of terminal Q of FF 74 is PF 71
The state of terminal 0 of each FF changes as shown in FIG. 4(a).
ここで、第４図（ａｌに示す様に正常動作をしている際
、００００の状態の時に外部雑音により００１０の状態
に変化したとすると、第４図（ｂｌに示す様に入カクロ
ソクの立上りでこの状態が１００１に遷移する。Here, when the state is 0000 during normal operation as shown in Figure 4 (al), it changes to the state 0010 due to external noise. This state changes to 1001.
そこで、ＦＦ７１．７２の端子Ｑの１０とＦＦ ７３．
７４の端子０の０１とがそれぞれ排他的論理和回路（以
下、 ＥＸ−ＯＲ回路と省略する）８１．８２に加えら
れてＩＥＸ−ＯＲが取られ、共に１がナンド回路８３に
加えられ、ここからＯがアンド回路６に加えられるので
第３図−■のクリアが加えられずＯが反転付き端子ＣＬ
Ｒに加えられるのでＦＦ ７１〜７４がクリアされて０
０００になり、第４図（ａｌの正常動作の方に移る。Therefore, 10 of terminal Q of FF71.72 and FF73.
The terminals 0 and 01 of 74 are respectively added to exclusive OR circuits (hereinafter abbreviated as EX-OR circuits) 81 and 82 to perform IEX-OR, and both 1 is added to the NAND circuit 83, where Since O is added to the AND circuit 6, the clear in Figure 3-■ is not added and O becomes the inverted terminal CL.
Since it is added to R, FF 71 to 74 are cleared and become 0.
000 and moves to the normal operation of FIG. 4 (al).
ここで、異常動作が検出される点は第４図（ｂｌの＊印
の部分でｏｏｏｏに復旧することが可能である。Here, the point where the abnormal operation is detected is the part marked with * in Fig. 4 (bl), and it is possible to recover to oooo.
これは第４図（ａｌに示す様に初期値がｏｏｏｏの時に
は１ビットずつシフトしてもＦＰ ７１．７２ とＦＦ
７３との端子０が共に１．０になることはない。As shown in Figure 4 (al), when the initial value is oooo, even if you shift it one bit at a time, FP 71.72 and FF
73 and terminal 0 will never both be 1.0.
しかし、異常動作の場合には第４図（ｂｌの＊印に示す
様に共に１０になることがある。そこで、この共に１０
になることを検出すれば異常動作をしていることが判る
。However, in the case of abnormal operation, both values may become 10 as shown in the * mark in Figure 4 (bl).
If this is detected, it can be determined that abnormal operation is occurring.
しかも、１つの状態遷移に対して検出可能点が４個所も
あるので復旧も早くなる。Moreover, since there are four detectable points for one state transition, recovery is also faster.
第５図は本発明の別の実施例のブロック図、第６図は第
５図の状態遷移図である。尚、ＦＦが７１〜７５と１段
増加し、１０分周のリングカウンタ回路になっている。FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a state transition diagram of FIG. Note that the number of FFs is increased by one stage to 71 to 75, making it a ring counter circuit with a frequency divided by 10.
又、異常動作検出手段は第２図と同じである。Further, the abnormal operation detection means is the same as that shown in FIG.
この場合の異常動作の状態遷移は第６図（ｂｌに示す様
に３種類あるが、いずれの場合でも前記と同じく異常動
作の際には２組のＦＦの出力状態が共にで検出してＰＦ
７１〜７５をクリアすれば従来よりも短時間にｏｏｏｏ
ｏに復旧させることができると共に、異常動作検出手段
は前記と同じ回路規模でよい。尚、１２分周のリングカ
ウンタ回路も共通な異常動作検出手段で実現可能である
。In this case, there are three types of abnormal operation state transitions as shown in Figure 6 (bl), but in any case, as in the case of abnormal operation, the output states of the two sets of FFs are detected together and the PF
If you clear 71-75, it will be done in a shorter time than before.
o, and the abnormal operation detection means may have the same circuit scale as described above. Note that a ring counter circuit with a frequency divided by 12 can also be realized using a common abnormal operation detection means.
以上詳細に説明した様に本発明によれば正常動作への復
旧時間が短縮されると共に、回路規模の増加も改善され
ると云う効果がある。As described in detail above, the present invention has the advantage of shortening the time required to restore normal operation and also reducing the increase in circuit scale.
第１図は本発明の原理ブロック図、
第２図は本発明の実施例のブロック図、第５図は本発明
の別の実施例のブロック図、第６図は第５図の状態遷移
図、
第７図は従来例のブロック図、
第８図は第７図のタイムチ士−ト、
第９図は第７図の状態遷移図を示す。
図において、
７はリングカウンタ回路、
８ば５％常動作検出手段を示す。
○Ｑ６）■＠■
Ｃ３−ｕFig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 5 is a block diagram of another embodiment of the invention, and Fig. 6 is a state transition diagram of Fig. 5. , FIG. 7 is a block diagram of the conventional example, FIG. 8 is a time chart of FIG. 7, and FIG. 9 is a state transition diagram of FIG. 7. In the figure, 7 indicates a ring counter circuit, and 8 indicates a 5% normal operation detection means. ○Q6)■@■ C3-u
Claims (1)
回路（７）において、 それぞれ所定個数のフリップフロップの出力が定められ
た状態になっていることを検出した時、該リングカウン
タ回路をクリアする信号を送出する異常動作検出手段（
８）を付加したことを特徴とするリングカウンタ回路。[Claims] In a ring counter circuit (7) in which flip-flops are connected in a ring, when it is detected that the outputs of a predetermined number of flip-flops are in a predetermined state, the ring counter circuit is activated. Abnormal operation detection means (
8) A ring counter circuit characterized by adding:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61266175A JPS63120523A (en) | 1986-11-07 | 1986-11-07 | Ring counter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61266175A JPS63120523A (en) | 1986-11-07 | 1986-11-07 | Ring counter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63120523A true JPS63120523A (en) | 1988-05-24 |
Family
ID=17427304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61266175A Pending JPS63120523A (en) | 1986-11-07 | 1986-11-07 | Ring counter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63120523A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002176354A (en) * | 2000-12-08 | 2002-06-21 | Mitsubishi Electric Corp | Semiconductor device |
-
1986
- 1986-11-07 JP JP61266175A patent/JPS63120523A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002176354A (en) * | 2000-12-08 | 2002-06-21 | Mitsubishi Electric Corp | Semiconductor device |
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