JPH0232645B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a clock disconnection detection method for monitoring status information generated by an external circuit and an external clock and detecting a clock disconnection in a circuit using a microprocessor. It is something.

(Prior Art) Fig. 1 shows a conventional example, and is a block diagram showing an example of the configuration of a circuit that uses a microprocessor to create a signal synchronized with an external clock.
μ-CPU uses a stored program format,
A microprocessor is responsible for various calculations, and I/O is an input/output device that handles input and output of various data.
This device is connected to a microprocessor μ-CPU via an address bus A-BUS and a data bus D-BUS. Also, F/F1 and F/F2 are D
An edge trigger type flip-flop.
F/F1 is for creating a synchronization signal, and F/F2 is for status informing the microprocessor μ-CPU of the clock status.

Figure 2 is a time chart of the circuit shown in Figure 1. In the figure, A indicates an external clock consisting of a pulse train of a ₀ , a ₁ , a ₂ , a _{3 .} . . , and B indicates the input/output. D indicates the output signal of the device I/O, D indicates the synchronization signal generated by the flip-flop F/F1, S indicates the status signal generated by the flip-flop F/F2, and R indicates the reset signal.

The operation of forming a signal synchronized with an external clock will be described below with reference to FIGS. 1 and 2.

In the configuration shown in FIG. 1, the output signal B shown in FIG. 2 is set to "H" level from the input/output device I/O to flip-flops F/F1 and F/F2 by a command from the microprocessor μ-CPU. When sent out as a signal, the subsequent signal a ₁ of external clock A
With the arrival of the external clock A, the flip-flop F/F1 generates a synchronizing signal D, and the flip-flop F/F2 generates a status signal S indicating the state of the external clock A. Thereafter, the microprocessor μ-CPU reads the status signal S generated and output from the flip-flop F/F2 via the input/output device I/O, and if it is at "H" level, the synchronization signal D is sent from the flip-flop F/F1. is being sent. After this determination, the microprocessor .mu.-CPU sets the output signal B, which had been sent out so far, to the "L" level, and sends out the reset signal R, thereby performing control to return to the initial state.

FIG. 3 is a flowchart showing the procedure of the operation described above.

However, in the control configuration as described above, if the external clock A does not arrive or disappears due to some failure, the synchronization signal D and the status signal S cannot change to the "H" level. The "status read" process flow in the flowchart shown in FIG. 3, in other words, the processes at and in the figure are repeated. That is, there were problems such as the microprocessor μ-CPU falling into a state as if it had stopped.

(Objective of the Invention) The present invention has been made in consideration of the above points, and it is possible to prevent the microprocessor from falling into a state as if it were stopped even if the external clock disappears due to a cause such as a failure. The purpose is to prevent this and allow other processing routines to process.

(Structure of the Invention) In other words, the device is configured to count the number of times the status signal is read, and when the value reaches a preset certain number of times, it is determined that the clock is disconnected and the process moves to the next process. to achieve the purpose of Hereinafter, the present invention will be explained in detail using the drawings.

(Embodiment of the invention) FIG. 4 is a block diagram explaining the clock interruption detection method according to the present invention. In the figure, ALU is a logic operation circuit and REG is a register, which is built in the microprocessor μ-CPU be done. others,
I/O, A-BUS, D-BUS, F/F1 and F/
F2 is an input/output device, an address bus, a data bus, and a flip-flop, respectively, and their configurations are the same as in the case of FIG. 1.

FIG. 5 is a flowchart showing the operating procedure of the external clock disconnection detection method according to the present invention. This shows the process of setting the

Here, the number of times the above status is read is:
It is a value determined by the clock frequency of the microprocessor μ-CPU and the frequency of the external clock.
In the time chart shown in Figure 2, the worst case is that the output signal B of the input/output device I/O is sent immediately after the external clock A (in this case, the time until the status becomes "1" is the external clock 1). (corresponding to the number of cycles).
Calculate in advance how many times the series of processes indicated by ~ in Figure 5 can be repeated within one cycle of the incoming external clock A, select a value that is greater than that number of times, and set it in the register REG. It turns out. Below, Figure 4, Figure 5 and Figure 2
The operation will be explained using figures.

That is, in the above set state, the microprocessor μ-CPU sends the output signal B shown in FIG. 2 as an "H" level signal to the flip-flops F/F1 and F/F2 via the input/output device I/O. Then, the logic operation circuit ALU of the microprocessor .mu.-CPU repeats the processing shown by .about. in FIG. 5 as a series of operations. After that, when clock _a1 of external clock A arrives at flip-flops F/F1 and F/F2, synchronization signal D is sent from flip-flop F/F1.
At the same time, the status signal S from the flip-flop F/F2 changes from the "L" level to "H".
level and is sent to the input/output device I/O.
This changed status signal S is read by the microprocessor μ-CPU and is sent to the logic operation circuit.
After the calculation in the ALU, the output signal B from the input/output device I/O is set to "L" level, and at the same time, a command is issued to the input/output device I/O to send a reset signal. By sending this reset signal R, the status signal S becomes "L" level. Since the output signal B from the input/output device I/O is at the "L" level, the synchronization signal D changes to the "L" level with the arrival of the next clock _a2 of the external clock A. This means that a signal (pulse) with a width of one clock synchronized with external clock A can be obtained.

Here, in the above series of processing operations, if the external clock A disappears due to the occurrence of some kind of failure and there is no arrival, the logic operation circuit ALU of the microprocessor μ-CPU repeats the processing shown in FIG. 5 above. It turns out. Then, when the number of repetitions exceeds the value preset in the register REG as described above, it is determined that the external clock has failed. In other words, when the set value of the register REG becomes "zero", the logic operation circuit ALU determines that the external clock has been disconnected, and the subsequent processing is performed by the fifth clock.
As shown in the figure, the process moves to step 1, performs processing when the clock is cut off, and then proceeds to the next step.

In this way, even if the clock is cut off due to disappearance of the external clock due to a failure or the like, processing continues without affecting the operation of the entire system, so the microprocessor can be used effectively.

FIG. 6 is a flow chart showing the operating procedure of another example of the clock interruption detection method according to the present invention, and FIG. 7 shows a time chart at that time.

In this example, another register function is added in addition to the register (REG) in the embodiment described using FIGS. 4 and 5. With this configuration, an example will be shown in which the synchronization signal to be created can be selected to have an arbitrary pulse width n times that of the external clock. In detail,
When creating a synchronizing signal D with a desired pulse width, for example twice the pulse width of external clock A shown in FIG. 7 as an example, set "2" in register A as shown in the process of FIG. 6. . After this, the logic operation circuit ALU performs the processing of ~ in the same manner as in the embodiments described so far, and at that time, it determines whether the clock is disconnected. It is determined whether or not a synchronization signal has been sent, and a synchronization signal with a desired pulse width, in this case two clock widths, is obtained.

In this way, by adding and configuring the microprocessor μ-CPU shown in FIG. 4 with a register A (not shown) in addition to the register REG, according to the operating procedure shown in FIG. It is possible to obtain a synchronizing signal with a width of 100 kHz, and also to judge and process clock disconnections, so that the same effects as in the previous embodiment can be expected.

(Effects of the Invention) As described above in detail, according to the present invention, even if there is a clock disconnection failure due to the disappearance of the external clock, the microprocessor is stopped (actually, the process of the status reading flow is executed). This is expected to have the effect of allowing other processing routines to be processed without having to do so.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of the configuration of a conventional signal generation circuit synchronized with an external clock, Figure 2 is a time chart of the circuit shown in Figure 1, and Figure 3 is the circuit shown in Figure 1. 4 is a block diagram showing one embodiment of the present invention, FIG. 5 is a flowchart of FIG. 4, FIG. 6 is a flowchart of another embodiment of the present invention, and FIG. 7 is a flowchart of another embodiment of the present invention. This is a time chart from that time. μ-CPU is a microprocessor, I/O is an input/output device, A-BUS is an address bus, D-BUS
is a data bus, F/F1 and F/F2 are flip-flops, ALU is a logic operation circuit, and REG is a register.

Claims (1)

[Claims] 1. In a circuit that uses a stored program format and uses a microprocessor that controls various operations to create a signal synchronized with an external clock, a first means for creating a signal synchronized with an external clock ( F/F1) and a second means (F/F1) for creating a status signal indicating the state of the external clock.
2), third means (I/O) for reading the status signal created by the second means into the microprocessor, fourth means (REG) for storing a preselected constant value; and a fifth means (ALU) that sequentially subtracts the values stored in the means, from the time when a signal synchronized with the external clock is created until the status signal is created by the second means. , the third and fifth main stages are repeated, and when the number of repetitions reaches a value set in the fourth means becomes zero, it is determined that an external clock has been interrupted.