JPH04101535A - Interface circuit - Google Patents

Abstract

PURPOSE:To protect erroneous operation of a system by preparing the system such that unless normal bit clock signal or data load signal is input, the output signal of a shift register cannot be ratched by a register. CONSTITUTION:When noise is mixed in a bit clock signal, since a counter 7 counts abnormally much, before a data load signal 5 reaches low level, a load enable signal 11 falls at low level, and when the data load signal 5 reaches low level, the load enable signal 11 goes up at high level. Further, when noise is mixed in the data load signal 5, since the data load signal 5 falls at low level before serial data signals are all transferred, the counter 7 is reset in the way of completing all the necessary counting. With this, the load enable signal 11 is left at high level and a clock signal 12 is also kept at high level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an interface circuit for inputting signals such as microcomputer commands in a digital signal processing circuit.

(Prior Art) FIG. 3 shows a configuration example of a conventional interface circuit, where l is a serial data signal, which is applied to a shift register 3 that is sequentially shifted by a bit clock signal 2. 4 is a register for latching the output of the shift register 3 in response to the falling edge of the data load signal 5;

FIG. 4 is a diagram showing the timing of each signal in the interface circuit of FIG. 3 above. First, the serial data signal 1 is sequentially shifted by the bit clock signal 2 and stored in the shift register 3. After all bit signals have been stored, the data load signal 5 is lowered from high level to low level to shift the data into the shift register 3. The output of 3 is latched into register 4. This behavior causes
The serial data signal l is converted into a parallel output 6 which is subjected to serial-to-parallel conversion.

FIG. 5 is a timing diagram when noise is mixed into the bit clock signal 2 and data load signal 5. Fifth
In the figure, for example, there is a noise n in the bit clock signal 2.
When 1 is mixed in as shown in the figure, D data is punched out twice by bit clock signal 2, as it should be. l DI
l DIl D,, The one that outputs the parallel data of DJ is Dll D,, D,.

Incorrect parallel data such as D, , D4 will be output.

Also, if noise n is mixed into the data load signal 5, it is normal. , D,, D,, D,, D, where parallel data should be output.

D4. Incorrect parallel data such as D,, D,, D, and correct parallel data, Do, D,, D,, D,, D, are output.

(Problems to be Solved by the Invention) As described above, in conventional interface circuits, when noise is mixed into the bit clock signal or data load signal, incorrect parallel data is output, causing the system to malfunction. Ta.

In view of the above, an object of the present invention is to provide an interface circuit that does not output erroneous parallel data even when noise is mixed into a bit clock signal or a data load signal.

(Means for Solving the Problems) The present invention achieves the above object by providing a shift register that sequentially shifts a serial data signal using a bit clock signal;
a counter that counts the number of bit clock signals; and a register that latches the output of the shift register when the counter counts a predetermined value and the data load signal enters a load enable state. This is achieved by latching the output of the shift register only when the bit clock signal is applied a regular number of times and then the data load signal enters the load enable state.

(Function) According to the interface circuit of the present invention, the output of the shift register is not latched into the register unless a regular bit clock signal or data load signal is input. Therefore, even if noise is mixed into the bit clock signal or data load signal, incorrect parallel data will not be output, and correct parallel data will always be output.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, shift register 3 and register 4 are the third
It is the same as shown in the figure, and the other reference numeral 7 is a counter for counting the number of rising edges of the bit clock signal 2, and its output is reset by the rising edge of the data load signal 5. 8 is a decoder, and 9 is an OR gate. The decoder 8 detects that the output IO of the counter 7 has reached a specific value, and outputs a load enable signal 11. The OR gate 9 outputs a low level only when the load enable signal 11 and the data load signal 5 are both low level.

The present invention is constructed as described above, and FIG. 2 shows the timing of the signals of each part thereof. First, the counter 7 is reset by the rising edge of the data load signal 5. Thereafter, each time the bit clock signal 2 rises, the counter 7 is incremented. In the example shown in FIG. 2, 5 bits of data are being transferred, so when the output lO of the counter 7 becomes 5, the load enable signal 11 becomes low level, ie, in an enabled state. At this time, when the data load signal 5 becomes low level, the output of the OR gate 9, that is, the clock signal 12 of the register 4 falls, and the output of the shift register 3 is latched into the register 4.

When the data load signal 5 rises again from low level to high level, the counter 7 is reset. In the configuration shown in FIG. 1 that operates in this way, if noise n, (FIG. 2) is mixed into the bit clock signal 2, the counter 7 will count more than normal, and the data load signal 5 will become low level. When the load enable signal 11 previously became low level and the data load signal 5 became low level, the load enable signal 1
1 becomes a high level, so the clock signal 12 of the register 4 remains at a high level, and erroneous data is not latched.

Furthermore, if noise n4 is mixed into the data load signal 5, the data load signal 5 becomes low level before all 5-bit serial data signals are transferred, and the counter 7 is reset midway. Therefore,
While the load enable signal 11 remains at a high level, the clock signal 12 of the register 4 also remains at a high level.

Therefore, in this case as well, incorrect data will not be latched.

(Effects of the Invention) As described above, the present invention includes a shift register for sequentially shifting a serial data signal using a bit clock signal, a counter for counting the bit clock signal, and a counter whose count value is a preset value. and a register that latches the output of the shift register only when the data load signal is in a load enable state, and a regular number of bit clock signals are input,
After that, the output of the shift register is latched only when the data load signal enters the load enable state, so the output of the shift register is latched only when a regular bit clock signal or data load signal is input. Since it is latched into a register, even if noise enters the bit clock signal or data load signal, incorrect parallel data will not be output, and incorrect command data will not be latched in the interface circuit of the microcontroller. Since malfunctions of the system are eliminated, the effect of using it in digital signal processing circuits, etc. is significant.

[Brief explanation of the drawing]

FIG. 1 is an interface circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the timing of each part signal in FIG. 1, FIG. 3 is a diagram showing an example of a conventional interface circuit, and FIG. FIG. 3 is a diagram showing the timing of each part signal when normal data is transferred, and FIG. 5 is a diagram showing the timing of each part signal when bit noise is mixed in in FIG. 4. 3...Shift register, 4...Register, 7.
...Counter, 8...Decoder, 9...OR
Gate. Patent applicant Matsushita Electric Industrial Co., Ltd.

Claims (1)

[Claims] A shift register that sequentially shifts a serial data signal using a bit clock signal, a counter that counts the number of bit clock signals, and a counter that counts a preset value, and an input data load signal that is in a load enable state. Only when
An interface circuit comprising: a register that latches the output of the shift register;