JP2748765B2 - Majority circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a majority circuit which performs a majority decision on three digital data and outputs normal output data.

[0002]

2. Description of the Related Art Conventionally, a majority decision circuit of this type has a circuit structure as shown in FIG. Reference numerals 17 to 19 denote input terminals to which the 1-bit data D _{1 to} D ₃ are input, respectively.
20 to 22 are AND gates, and 23 is an OR gate.
The AND gate 20 receives the data D from the input terminals 17 and 19.
₁ and D ₃ are input, and the AND gate 21 has an input terminal 1
7 and 18 data D ₁ and D ₂ are input from, the AND gate 22 from the input terminal 18 and 19 D ₂ and D ₃ are input, the output from these ANDO gate 20-22 OR
The data is input to the gater 23. And O
The majority decision result data D is output from the R gate 23 to the output terminal 24.
Is output to FIG. 3 shows the relationship between the data D ₁ , D ₂ , D ₃ and the majority decision data D in the majority circuit. That is, if there are many “0” s among the input data D _{1 to} D ₃ , majority decision result data D of “0” is output, and if there are many “1s” among the data D _{1 to} D ₃ ,
The data D of “1” is output.

[0003]

[0006] Conventional majority circuit described above, among the three input data D ₁ to D _3, even if incorrectly one data, if the other two data are normal, normal And outputs the majority decision result data D. However, if one of the input data D _{1 to} D ₃ is incorrect and one of the other two data has an error, and only one normal data is present, ,
The output data D has an incorrect value in most cases. That is, only when one of the two erroneous data is an error fixed to “1” and the other data is fixed to “0”, the output data D is accidentally set to normal. In other cases, the output data D has an incorrect value. In particular, if the two data errors occur randomly, it is unlikely that the output data D will always take a normal value.
In such a case, the output data D is almost 100% probable.
Is considered to cause an error.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has been made to increase the probability of outputting normal output data even when an error occurs in two of the three input data. It is intended to provide a circuit.

[0005]

In order to achieve the above object, the present invention provides a first detecting circuit for detecting a mismatch between first data and second data among first to third data. A second detection circuit for detecting a mismatch between the first data and the third data; and a first detection circuit when none of the first and second detection circuits detects the mismatch.
And outputs the first data when either of the first or second detection circuit detects the inconsistency, and both of the first and second detection circuits output When the mismatch is detected, the second data is output.

[0006]

According to the present invention, when the first data and the second data do not match, that fact is detected by the first detection circuit, and when the first data and the third data do not match, the fact is detected. , The fact is detected by the second detection circuit. When neither the first nor the second detection circuit detects a mismatch, the first data is output from the output circuit,
The first data is output from the output circuit when either the first or the second detection circuit detects a mismatch, and the second data is output when both the first and the second detection circuits detect a mismatch. Is output.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a majority circuit according to one embodiment of the present invention. 1 to 3 are input terminals from which 1-bit data D _{1 to} D ₃ are respectively output, and input terminals 1 and 2 are EXCLUSIVE-
OR gate 4, input terminals 1 and 3 are EXCLUSIVE
-Connected to OR gate 5. As a result, the discrepancy detection between the values of the data D ₁ and the data D ₂ is determined by EXCLUSIV.
Performed by E-OR gate 4, mismatch detection data D ₁ and data D ₃ is EXCLUSIVE-OR gate 5
It is performed by The outputs of the EXCLUSIVE-OR gates 4 and 5 are both EXCLUSIVE-OR gates 6
And the NAND gate 7.

Reference numeral 9 denotes a D flip-flop (D-FF) which can hold the state when only the value of the data D ₂ or D ₃ is incorrect. E via the inverter 8
The output terminal of the XCLUSIVE-OR gate 6 is connected. 12 D flip-flops (D-F, which can retain its state if only the value of the data D ₁ is incorrect
F), and the preset input terminal is connected to the output terminal of the NAND gate 7 and the Q output terminal of the D flip-flop 9. Here, reference numeral 11 denotes a reset input terminal for a reset signal. The reset input terminal 11 is connected to the clear input terminals of the D flip-flops 9 and 12. Therefore, in the initial state initialized by the reset signal, the value of the Q output of the D flip-flops 9 and 12 is “0”.
Becomes 13 is an AND gate connected to the input terminal 1 of the inverting Q output terminal and D ₁ data of the D flip-flop 12, 14 is an input terminal 2 for the Q output terminal and D ₂ data of the D flip-flop 12 Is connected to an AND gate. The AND gates 13 and 14 are connected to an OR gate 15, and the OR gate 15 outputs majority decision result data D to an output terminal 16. Therefore, the AND gates 13 and 14 and the OR gate 15
When the value of the Q output of the flip-flop 12 is “0”, the value of the input data D ₁ is output as the output data D, and “1”
And outputting the value of the input data D ₂ as the output data D in the case of. It is assumed that the input data D _{1 to} D ₃ change at the same timing, and EXCLUS
It is assumed that glitch noise does not occur in the IVE-OR gates 4 to 6 and the NAND gate 7.

Next, the operation of this embodiment will be described.
First, a case where the values of the input data D _{1 to} D ₃ are all equal will be described. In a state initialized by the reset signal of the reset input terminal 11, all the input data D _{1 to} D ₃
Has no error and the data (D ₁ , D ₂ , D ₃ ) = (1,
If (1, 1) is input to input terminals 1 to 3, EX
The CLUSIVE-OR gates 4 and 5 output a signal of "0" indicating coincidence. For this reason, EXCLUS
A signal of “0” is output from the IVE-OR gate 6, and
A signal of “1” is input to the preset input terminal of the D flip-flop 9, and a signal of “0” is output from the Q output terminal of the D flip-flop 9 in the initial state. On the other hand, since a signal of “1” is output from the NAND gate 7 and a signal of “0” is input to the preset input terminal of the D flip-flop 12, the D flip-flop 1
2 from the Q output terminal and the inverted Q output terminal are “0” and “1”, respectively.
Is output. Therefore, the AND gate 13,
The output data D output from the OR gate 15 to the output terminal 16 via 14 indicates the same “1” as the value of the input data D. Similarly, data (D ₁ , D ₂ , D ₃ ) = (0, 0,
0) is input to the input terminals 1 to 3, the Q output of the D flip-flop 12 becomes "0" and the output terminal 16
The outputs output data D of the same "0" and the data D _1.

Next, _one of the values of the input data D _{1 to} D ₃ is set to 1
A case will be described where an error occurs in one input data and this data takes a value different from the remaining two input data.
The data (D ₁ , D ₂ , D ₃ ) = (1, 1) while being initialized by the reset signal at the reset input terminal 11.
(1, 0) is input to the input terminals 1 to ₃ (an error occurs in the data D3). From EXCLUSIVE-OR gate 4 and 5, each indicating a match of the data D ₁ and D ₂ "0", a signal "1" indicating the disagreement of the data D ₁ and D ₃ are output. Therefore, a signal of “1” is output from the EXCLUSIVE-OR gate 6, a signal of “0” is input to the preset input terminal of the D flip-flop 9, and “1” is output from the Q output terminal of the D flip-flop 9. Is output. Therefore, from the OR gate 10,
Regardless of the output value of NAND gate 7, a signal of "0" is always output. Therefore, the values of the Q output and the inverted Q output of the D flip-flop 12 are fixed to “0” and “1”, respectively, unless a reset signal is input. As a result,
As long as the reset signal is not input, the data D 16 is output from the output terminal 16 regardless of the values of the input data D _{1 to} D _3.
Output data D of the same value "1" and ₁ is output.

In the above state, the input data D ₂
Error occurs and the normal input data becomes only the data D ₁ , the output data D
Shows the same value "1" and the input data D _1. However, an error occurs in the input data D _1, the normal input data is data D
When the number becomes only ₂ , the output data D indicates an incorrect value “0”. That is, when an error occurs in one of the remaining input data D ₁ and D ₂ after an error occurs in the input data D ₃ , the probability that the output data D takes a normal value is 5
0%. The same probability exists when an error occurs in _{one of the} remaining input data D ₁ and D ₃ after an error occurs in the input data D ₂ .

Finally, the data (D ₁ , D _1)
(2 , D ₃ ) = (0, 1, 1) is input to the input terminals 1 to 3 (an error occurs in the data D ₁ ).
The EXCLUSIVE-OR gates 4 and 5 output a signal of “1” indicating a mismatch. For this reason, EX
The signal “0” is output from the CLUSIVE-OR gate 6, and the signal “0” is output from the Q output terminal of the D flip-flop 9 in the initial state. On the other hand, NAN
Since a signal of "0" is output from the D gate 7 and a signal of "0" is output from the OR gate 10, "1" is output from the Q output terminal and the inverted Q output terminal of the D flip-flop 12, respectively. , "0" are output. At this time, the Q output value and the inverted Q output value of the D flip-flop 12 are fixed to the above values unless reset. Thus, thereafter, as long as the reset signal is not input from the output terminal 16, regardless of the value of the input data D ₁ to D _3, the output data D of the same value "1" and the data D ₂ are output.

In the above state, the input data D
₃ errors occur in the case where the normal input data becomes only the data D ₂ also, the output data D from the output terminal 16 has the same value "1" and the input data D _2. However, an error occurs in the input data D _2, when a normal input data becomes only the data D _3, the output data D indicates an incorrect value "0". That is, when an error occurs in one of the remaining input data D ₂ and D ₃ after an error occurs in the input data D ₁ , the probability that the output data takes a normal value is 5
It becomes 0%.

As described above, in the majority circuit of this embodiment, after an error occurs in any _one of the input data D _{1 to} D ₃ , an error occurs in one of the remaining input data. Output data D is 50%
It will take a normal value with the probability of. Therefore, FIG.
In the conventional majority decision circuit shown in FIG. 5, when the error occurs in the second input data, the probability that the output data D takes a normal value is almost 0%. The probability of a correct answer at is significantly large.

[0015]

As described above, according to the present invention, even when an error occurs in two of the first to third data, a normal value is output with a probability of 50%. Therefore, there is an excellent effect that a very accurate majority operation is performed and product performance is improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a majority decision circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional majority circuit.

FIG. 3 is a table showing a relationship between input data and output data by a conventional majority circuit.

[Explanation of symbols]

 1-3 input terminals 4-6 EXCLUSIVE-OR gate 7 NAND gate 8 inverter 9, 12 D flip-flop 10, 15 OR gate 13, 14 AND gate 16 output terminal

Claims (1)

(57) [Claims] A first detection circuit for detecting a mismatch between the first data and the second data among the first to third data; and a mismatch between the first data and the third data. A second detection circuit for detecting the inconsistency, and when none of the first and second detection circuits detects the inconsistency, outputs the first data, and outputs the first data from the first or second detection circuit. An output that outputs the first data when either of them detects the mismatch, and that outputs the second data when either of the first and second detection circuits detects the mismatch. And a majority decision circuit.