JPS6111492B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to an error detection circuit for a decoder.

As shown in FIG. 2, the conventional decoder error detection circuit has a configuration in which an odd-even check circuit 2 is connected to the output of a decoder 1, and the decoder output formed from the logic "1" state of even numbered bits is Errors are displayed only when they occur.

However, there is a drawback in that when a failure in the decoder 1 causes an output in which only a bit is in the logical "1" state at a position other than the intended output, an error cannot be displayed and the output is treated as normal.
In addition, in another configuration, a method was adopted in which a decoder was installed twice and a decoder error was detected by comparing the outputs of the two decoders. This method has the disadvantage that a large number of comparators are required, which increases the number of circuit elements.

The purpose of the present invention is to eliminate decoder errors in which bits in the logic "1" state are output at positions other than the intended output due to a one-bit error, and decoder errors in which a pattern in which even-numbered bits are in the logic "1" state are output. An object of the present invention is to provide a decoder error detection circuit that can detect errors with a small number of elements.

The circuit of the present invention includes a decoder that decodes an N-bit input signal and makes only one of the ^2N -bit signals a logic signal "1", and a ^2N- bit signal that is the output of this decoder. an odd-even test circuit that performs an odd-even test on signals; a selection circuit that selects one signal from the 2 ^N- bit signals provided from the decoder based on an N-bit input signal provided to the decoder; and a circuit that outputs an error detection signal when an abnormality is detected in at least one of the output from the selection circuit and the output from the selection circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1A shows a commonly used decoder 1. Terminals G ₁ and G ₂ are enable terminals of the decoder. The binary signals applied to input terminals A, B, and C are decoded according to the weight assigned to each bit, and one of the outputs 0 to 7 is displayed as a logic "1" state. Ru. The output position is OUT=2 ⁰・A+2 ¹・B+2 ²・C 〓〓〓〓
An example thereof is shown in FIG. 1B.
“X” indicates that it can be either logic “1” or logic “0”. Assuming that a failure occurs somewhere inside the decoder, the output of the decoder can be in the following two states.

First state: 2 bits of output are logic “1”
(on) state.

Second state: 1 bit of the output is logic “1”
(on) state, but output is generated at the wrong position.

The decoder error detection circuit shown in FIG. 2 can detect the first state, but cannot detect the second state.

FIG. 3 is a diagram showing an embodiment of the present invention. Binary data to be decoded is applied to the input terminals of the decoder 100 via terminals A, B and C, and is also applied to the signal selection circuit 102 as a selection designation input signal 201. Output lines 210, 211, 212, 213, 21 of decoder 100
4, 215, 216 and 217 are applied to the input terminal of the odd-even check circuit 101, and are also applied to the signal input terminal of the signal selection circuit 102 as the input signal 206 to be selected. When the decoding state of the decoder is normal, the number of logic "1"s of the input signal 205 given to the odd-even check circuit 101 is an odd number, so the output signal 20 of the odd-even check circuit 101 is
7 becomes logic "1". On the other hand, the signal selection circuit 102
The selection designation input signal 201 is given a signal before being decoded as described above, and the input signal 206
Only one specified bit in the output signal 208
is output as At this time, if the decoding state of the decoder 100 is normal, the output signal 208 of the signal selection circuit 102 becomes logic "1", and this output signal 20
The output signal 209 of the NAND circuit 104 to which 8 is applied becomes logic "0", indicating that it is normal.

Now, assume that the decoder produces an output at the wrong position. At this time, the signal at the position where the decoder should originally output becomes logic "0" and one signal at the other erroneous position becomes logic "1". For this reason, the output signal 207 of the odd-even check circuit 101 is treated as logic "1" and normal, but the output signal 208 of the signal selection circuit 102 is a decoder at the position specified by the selection designation input signal 201 that should be output. The output signal 208 becomes a logic "0", and the output signal 209 of the NAND circuit 104 becomes a logic "1", indicating an error in the decoder. Decoder 10 due to failure of another decoder.
When 2n bits of the 0 outputs become logic "1" or when all of the outputs of the decoder 100 do not become logic "0", the output 207 of the odd-even check circuit 101 becomes logic "0". circuit 1
The output 209 of 04 becomes logic "1" and it is detected that the output of the decoder 100 has an error.

Although one embodiment of the present invention has been described above, the configuration of the decoder is not limited to one with a 3-bit input, but can also be realized with a decoder with other bit configurations, and only one bit of the output of the decoder becomes logic "0". This can be easily realized using a decoder such as

In the present invention, by connecting an odd-even check circuit and a signal selection circuit to the output of the decoder, it is possible to detect errors in which the decoder output is decoded to another erroneous position and errors in which the decoder output is duplicated, with a small number of elements. There is an effect.

[Brief explanation of drawings]

1A and 1B are diagrams showing a generally used decoder and the truth value state of its output, FIG. 2 is a diagram showing a conventional decoder error detection circuit, and FIG. 3 is a diagram showing an embodiment of the present invention. be. 1 to 3, A, B, C... decoder input terminals, 100... decoder, 101...
... Odd-even check circuit, 102 ... Signal selection circuit, 10
4...NAND circuit, 201...Signal selection designation input signal, 205...Odd-even check circuit input signal, 206
... Signal selection circuit input signal, 207 ... Odd number output signal, 208 ... Selection circuit output signal, 209 ...
Decoder error detection signal, 210-217...Decoder output signal. 〓〓〓〓

Claims (1)

[Claims] A decoder that decodes a 1N-bit input signal and makes only one of the ^2N- bit signals into a logic signal "1" state, and the output of this decoder is a ^2N- bit an odd-even check circuit that performs an odd-even test on the signals; a selection circuit that selects one signal from the 2 ^N- bit signals provided from the decoder based on an N-bit input signal provided to the decoder; An error detection circuit comprising a circuit that outputs an error detection signal when an abnormality is detected in at least one of the output from the test circuit and the output from the selection circuit.