JPS6134301B2

JPS6134301B2 -

Info

Publication number: JPS6134301B2
Application number: JP53081323A
Authority: JP
Inventors: Yasuhiro Nagayama
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1978-07-03
Filing date: 1978-07-03
Publication date: 1986-08-07
Also published as: JPS559262A

Description

【発明の詳細な説明】本発明はデコーダ回路の誤り検出回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error detection circuit for a decoder circuit.

従来、デコーダ出力の誤り検出は、第３図のよ
うに、デコーダ１００のの出力端子に接続した奇
偶検査回路１０１および１０２を用いて行なつて
おり、デコーダ１００の出力端子に偶数個の論理
“１”が生じた時に誤り表示をするようになつて
いる。しかし、デコーダ内部の構成要素等の故障
により目的とする１本の出力端子以外の１本の端
子に論理“１”出力が生じたときには誤り表示は
できず正常とみなされてしまう欠点がある。この
欠点を解決する構成として、デコーダを二重化し
てデコーダのそれぞれの出力を常に比較すること
によりデコーダの誤りを検出する方式がとられて
いるが、デコーダが二ついること、さらに、各出
力の数だけ比較器が必要となること等のため構成
が複雑化するという欠点がある。 Conventionally, error detection in decoder output has been performed using odd-even check circuits 101 and 102 connected to the output terminals of the decoder 100, as shown in FIG. 1” occurs, an error is displayed. However, if a logic "1" output occurs at one terminal other than the intended output terminal due to a failure of a component inside the decoder, there is a drawback that an error cannot be displayed and the decoder is regarded as normal. To solve this problem, a system has been adopted in which decoders are duplicated and decoder errors are detected by constantly comparing the outputs of each decoder. There is a drawback that the configuration becomes complicated because more comparators are required.

本発明の目的は１ビツト誤りによる目的外出力
を生じるデコーダ誤りを少ない素子数で検出でき
るようにしたデコーダ誤り検出回路を提供するこ
とにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder error detection circuit capable of detecting a decoder error that causes an unintended output due to a 1-bit error with a reduced number of elements.

本発明の回路は、Ｎビツト入力に応答して２^N
本の出力線のうちの１つの出力線に論理“１”を
出力するデコーダと、このデコーダに与えられる
Ｎビツト入力と同じ内容のＮビツト入力が与えら
れこの入力に対して奇偶検査を行なう第１の奇偶
検査回路と、それぞれ奇数個の論理“１”のビツ
トを有する２^(N-1)通りのＮビツト入力を正常な
前記デコーダに与えたとき論理“１”を出力する
２^(N-1)本の前記出力線が接続されこれら出力線
から得られる信号と前記第１の奇偶検査回路から
の偶数検出信号とに基づいて奇偶検査をする第２
の奇偶検査回路と、この第２の奇偶検査回路に接
続された前記出力線以外の２^(N-1)本の前記出力
線が接続されこれら出力線から得られる信号と前
記第１の奇偶検査回路からの奇数検出信号とに基
づいて奇偶検査をする第３の奇偶検査回路と、前
記第２の奇偶検査回路の検査結果および前記第３
の奇偶検査回路の検査結果に基づいて前記デコー
ダの複数本の出力線が論理“１”となる状態と誤
つた位置にある１本の出力線が論理“１”となる
状態とを検出する異常検出回路とから構成され
る。 The circuit of the present invention responds to an N-bit input with 2 ^N
A decoder that outputs logic "1" to one of the output lines of the main output line, and a decoder that is given an N-bit input with the same content as the N-bit input given to this decoder and performs an odd-even check on this input. 1 odd-even check circuit and 2 ^(N-1) types of N-bit inputs each having an odd number of logic "1" bits are applied to the normal decoder, which outputs logic "1" ^{. 1)} A second circuit to which the two output lines are connected and performs an odd-even test based on the signals obtained from these output lines and the even detection signal from the first odd-even test circuit.
and the 2 ^(N-1) output lines other than the output line connected to the second odd-even check circuit are connected to the signals obtained from these output lines and the first odd-even check circuit. a third odd-even test circuit that performs an odd-even test based on an odd detection signal from the circuit; and a test result of the second odd-even test circuit and the third
An abnormality that detects a state in which a plurality of output lines of the decoder become logic "1" and a state in which one output line in the wrong position becomes logic "1" based on the test results of the odd-even test circuit. It consists of a detection circuit.

本発明の特徴は、１ビツト誤りのうち誤り位置
の異なる誤りを検出するためある２進数とその２
進数の１ビツトのみを反転した２進数との関係
（以下ハミング距離“１”と称す）にある集団と
それ以外の集団に分け論理“１”の奇偶に応じて
前記２つの集団の状態を監視することにある。 A feature of the present invention is that a binary number and its binary number are used to detect errors with different error positions among 1-bit errors.
Divide into a group that has a relationship with a binary number in which only one bit of the base number is inverted (hereinafter referred to as Hamming distance "1") and other groups, and monitor the status of the two groups according to the oddness or evenness of the logic "1". It's about doing.

次に本発明を図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第１図は一般的なデコーダ１００を示す図であ
る。第１図に示す端子Ｇ１およびＧ２はデコーダ
回路のイネーブル端子であり、以下の説明では省
略する。端子Ａ，Ｂ，ＣおよびＤに与えられた２
進信号は解読されその解読結果は出力端子０から
15のうちのどれか１つの出力端子から送出され
る。デコーダ１００の内部のどこか一ケ所に故障
が生じたときには、デコーダ１００の出力は次の
２つの状態をとる。第１の状態では出力が２本生
じる。また、第２の状態では誤つた位転に出力が
生じる。 FIG. 1 is a diagram showing a general decoder 100. Terminals G1 and G2 shown in FIG. 1 are enable terminals of the decoder circuit, and will not be described below. 2 given to terminals A, B, C and D
The forward signal is decoded and the decoding result is output from output terminal 0.
It is sent from one of the 15 output terminals. When a failure occurs somewhere inside the decoder 100, the output of the decoder 100 takes on the following two states. In the first state, two outputs are produced. Further, in the second state, an output is generated at an erroneous position.

第２図に示す従来のデコーダ誤り検出回路の出
力パターンにおいては、第１の状態は検出できた
が第２の状態は検出不可能である。 In the output pattern of the conventional decoder error detection circuit shown in FIG. 2, the first state could be detected, but the second state could not be detected.

第４図は本発明の一実施例を示す図である。第
４図において端子Ａ，Ｂ，ＣおよびＤはデコード
されるべき２進信号を受けるとともにデコーダ１
００の入力端子に接続され、さらに、第１奇偶検
査回路１０３に接続されている。この奇偶検査回
路は入力信号の論理“１”の数が奇数の時に信号
線２０３が論理“１”、信号線２０４は論理
“０”となり、逆に入力信号の論理“１”の数が
偶数の時は信号線２０３が論理“０”、信号線２
０４は論理“１”となる回路である。 FIG. 4 is a diagram showing an embodiment of the present invention. In FIG. 4, terminals A, B, C and D receive the binary signal to be decoded and the decoder 1
00 input terminal, and further connected to the first odd-even check circuit 103. In this odd-even check circuit, when the number of logic "1"s in the input signal is odd, the signal line 203 becomes logic "1" and the signal line 204 becomes logic "0", and conversely, when the number of logic "1"s in the input signal is even When , the signal line 203 is logic “0” and the signal line 2 is
04 is a circuit with logic "1".

本発明の回路は、デコーダ１００、このデコー
ダ１００に与えられる４ビツトデータに基づいて
上述の奇偶検査をする第１の奇偶検査回路１０
３、それぞれ偶数個（０個も含む）の論理“１”
のビツトを有する８通りの４ビツトデータ（すな
わち、（0000），（0011），（0101），（0110），
（1001），（1010），（1100），（1111））を正常な前
記
デーコーダ１００に与えたときに論理“１”を出
力する８本のデコーダ１００の出力線が接続され
これら出力線から得られる信号と第１の奇偶検査
回路１０３からの奇数検出信号２０３とに基づい
て上述の奇偶検査をする第２の奇偶検査回路１０
１、第２の奇偶検査回路１０１に接続された前記
出力線以外の８本のデコーダ１００の出力線が接
続されこれら出力線から得られる信号と第１の奇
偶検査回路１０３からの偶数検出信号２０４とに
基づいて上述の奇偶検査をする第３の奇偶回路１
０２および前記第２の奇偶検査回路１０１からの
検査結果２０７と前記第３の奇偶検査回路１０２
からの検査結果２０８とのNAND論理をとり誤り
検出信号２０９を生じるNAND回路１０４から構
成されている。 The circuit of the present invention includes a decoder 100 and a first odd-even check circuit 10 that performs the above-mentioned odd-even check based on 4-bit data applied to the decoder 100.
3. Even number of logic “1” (including 0) for each
Eight types of 4-bit data (i.e., (0000), (0011), (0101), (0110),
(1001), (1010), (1100), (1111)) are connected to the output lines of the eight decoders 100 that output logic "1" when the normal decoder 100 is given the output lines. a second odd-even check circuit 10 that performs the above-mentioned odd-even check based on the signal and the odd-even detection signal 203 from the first odd-even check circuit 103;
1. Eight output lines of the decoder 100 other than the output line connected to the second odd-even check circuit 101 are connected, and signals obtained from these output lines and an even number detection signal 204 from the first odd-even check circuit 103 are connected. The third odd-even circuit 1 performs the above-mentioned odd-even test based on
02 and the test result 207 from the second odd-even test circuit 101 and the third odd-even test circuit 102
It is composed of a NAND circuit 104 which performs a NAND logic with the test result 208 from the above and generates an error detection signal 209.

次に本発明の動作について説明する。 Next, the operation of the present invention will be explained.

デコーダ１００が正常のときには第２奇偶検査
回路１０１の入力線２０５と第３奇偶検査回路１
０２の入力線との論理“１”の数はともに奇数で
あるため、第２および第３の奇偶検査回路の出力
線２０７および２０８はともに論理“１”となり
NAND回路１０４の出力線２０９は論理“０”と
なり、正常状態を表示する。誤つた出力位置に信
号が出る誤りのときには、１ビツト誤りであれば
ハミング距離“１”だけ離れた位置に出力される
ため、第２および第３奇偶検査回路の入力線２０
５および２０６の論理“１”の数は偶数となり第
２および第３奇偶検査回路の出力線２０７および
２０８は論理“０”となりNAND回路１０４の出
力２０９は論理“１”となり誤りを表示する。 When the decoder 100 is normal, the input line 205 of the second odd-even check circuit 101 and the third odd-even check circuit 1
Since the number of logic "1"s with the input line 02 are both odd numbers, the output lines 207 and 208 of the second and third odd-even check circuits are both logic "1".
The output line 209 of the NAND circuit 104 becomes logic "0", indicating a normal state. In the case of an error in which a signal is output to the wrong output position, if it is a 1-bit error, the signal is output to a position separated by a Hamming distance of "1", so the input line 20 of the second and third odd-even check circuits
The number of logic "1"s in the circuits 5 and 206 becomes an even number, and the output lines 207 and 208 of the second and third odd-even check circuits become logic "0", and the output 209 of the NAND circuit 104 becomes logic "1", indicating an error.

偶数個のデコーダ出力が論理“１”となる誤り
も第２および第３奇偶検査回路１０１および１０
２の入力線２０５または２０６の少なくともどち
らか一方の入力線の論理“１”の数が偶数となる
ため奇偶検査回路１０１または１０２の出力線２
０７または２０８の出力線が論理“０”となり
NAND回路１０４の出力２０９は論理“１”とな
り誤りを表示する。 An error in which an even number of decoder outputs become logic “1” is also detected by the second and third odd-even check circuits 101 and 10.
Since the number of logical "1"s on at least one of the input lines 205 and 206 of 2 is an even number, the output line 2 of the odd-even check circuit 101 or 102
07 or 208 output line becomes logic “0”
The output 209 of the NAND circuit 104 becomes logic "1", indicating an error.

以上本発明の一実施例について説明したがデコ
ーダの構成は４ビツトに限らず他の構成のもので
も可能である。また、第２および第１の奇偶検査
回路において奇数入力で、デコーダを正常とみな
す例を示したが偶数入力で正常とするように構成
も容易に実現できる。 Although one embodiment of the present invention has been described above, the configuration of the decoder is not limited to 4 bits, but other configurations are also possible. Further, although an example has been shown in which the decoder is considered normal when an odd number input is made in the second and first odd-even check circuits, a configuration in which the decoder is considered normal when an even number input is made can be easily realized.

以上、本発明には、正常時に出力されるデコー
ダ出力線とは異なるデコーダ出力線に論理“１”
が出力される誤りと２個の論理“１”が出力され
る誤りとを少ない回路素子数で検出できるという
効果がある。 As described above, in the present invention, logic "1" is applied to a decoder output line different from the decoder output line outputted during normal operation.
This has the effect that an error in which a ``1'' is output and an error in which two logic "1"s are output can be detected with a small number of circuit elements.

[Brief explanation of the drawing]

第１図は一般的なデコーダを示す図、第２図は
第１図のデータ入力と出力との真理値状態を示す
図、第３図は従来のデコーダ誤り検出回路を示す
図および第４図は本発明の一実施例を示す図であ
る。第１図から第４図において、Ａ，Ｂ，Ｃ，Ｄ…
…デコーダ入力端子、１００……デコーダ、１０
１……第２奇偶検査回路、１０２……第３奇偶検
査回路、１０３……第１奇偶検査回路、１０４…
…NAND回路、２０１……入力信号、２０３……
奇数出力信号、２０４……偶数出力信号、２０５
……第２奇偶検査回路入力信号、２０６……第２
奇偶検査回路入力信号、２０７……第２奇偶検査
回路奇数出力信号、２０８……第３奇偶検査回路
奇数出力信号、２０９……デコーダ誤り検出信
号、２１０〜２１５……デコーダ出力信号。 FIG. 1 is a diagram showing a general decoder, FIG. 2 is a diagram showing the truth value state of the data input and output in FIG. 1, FIG. 3 is a diagram showing a conventional decoder error detection circuit, and FIG. 4 is a diagram showing a conventional decoder error detection circuit. FIG. 1 is a diagram showing an embodiment of the present invention. In Figures 1 to 4, A, B, C, D...
...Decoder input terminal, 100 ...Decoder, 10
1... Second odd-even test circuit, 102... Third odd-even test circuit, 103... First odd-even test circuit, 104...
...NAND circuit, 201... Input signal, 203...
Odd number output signal, 204... Even number output signal, 205
...Second odd-even check circuit input signal, 206...Second
Odd-even check circuit input signal, 207... Second odd-even check circuit odd output signal, 208... Third odd-even check circuit odd output signal, 209... Decoder error detection signal, 210-215... Decoder output signal.

Claims

[Claims] A decoder that outputs logic "1" to one of ^2N output lines in response to a 1N-bit input; A first odd-even check circuit is provided with an ^N- bit input and performs an odd-even check on the input; The 2 ^(N-1) output lines that output logic "1" when applied to the decoder are connected, and based on the signals obtained from these output lines and the even detection signal from the first odd-even check circuit, A second odd-even test circuit that performs an odd-even test, and two ^(N-1) output lines other than the output lines connected to the second odd-even test circuit are connected to each other, and signals obtained from these output lines and a third odd-even test circuit that performs an odd-even test based on the odd-even detection signal from the first odd-even test circuit; and an abnormality detection circuit that detects a state in which a plurality of output lines of the decoder become logic "1" based on the logic "1" and a state in which one output line located in an incorrect position becomes logic "1". A decoder error detection circuit featuring: