JPS559262A - Detection circuit for decoder error - Google Patents

Detection circuit for decoder error

Info

Publication number
JPS559262A
JPS559262A JP8132378A JP8132378A JPS559262A JP S559262 A JPS559262 A JP S559262A JP 8132378 A JP8132378 A JP 8132378A JP 8132378 A JP8132378 A JP 8132378A JP S559262 A JPS559262 A JP S559262A
Authority
JP
Japan
Prior art keywords
odd number
output
input
decoder
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8132378A
Other languages
Japanese (ja)
Other versions
JPS6134301B2 (en
Inventor
Yasuhiro Nagayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8132378A priority Critical patent/JPS559262A/en
Publication of JPS559262A publication Critical patent/JPS559262A/en
Publication of JPS6134301B2 publication Critical patent/JPS6134301B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To detect the error decoded at wrong position and the error outputted to two portions, by discriminating the input data to the decoder for even and odd number and by separating the output of even and odd number for the humming distance of the decoder output.
CONSTITUTION: The data A to D to be decoded are inputted to the decoder 100 and inputted to the first even and odd number inspection circuit 103, and the output in which the humming distance among the outputs of 0 to 15 decoded is an even number is given to the second even and odd number inspection circuit 101 as the input 205, and the output in which the humming distance is an odd number is fed to the third even and odd number inspection circuit 102 as the input 206. The circuit 103 performs the check of even and odd number for the inputs A to D, and the odd number output TD and the even number TE are respectively inputted to the circuits 101 and 102. In case of an odd number output, TD and TE are respectively 0 and 1. When the decoder output is normal, the input to the NAND circuit 104 is 1, but if in error, at least one input is 0 to display error.
COPYRIGHT: (C)1980,JPO&Japio
JP8132378A 1978-07-03 1978-07-03 Detection circuit for decoder error Granted JPS559262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8132378A JPS559262A (en) 1978-07-03 1978-07-03 Detection circuit for decoder error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8132378A JPS559262A (en) 1978-07-03 1978-07-03 Detection circuit for decoder error

Publications (2)

Publication Number Publication Date
JPS559262A true JPS559262A (en) 1980-01-23
JPS6134301B2 JPS6134301B2 (en) 1986-08-07

Family

ID=13743181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8132378A Granted JPS559262A (en) 1978-07-03 1978-07-03 Detection circuit for decoder error

Country Status (1)

Country Link
JP (1) JPS559262A (en)

Also Published As

Publication number Publication date
JPS6134301B2 (en) 1986-08-07

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