JPS5642862A - Fault detecting system for electronic computer - Google Patents

Fault detecting system for electronic computer

Info

Publication number
JPS5642862A
JPS5642862A JP11900779A JP11900779A JPS5642862A JP S5642862 A JPS5642862 A JP S5642862A JP 11900779 A JP11900779 A JP 11900779A JP 11900779 A JP11900779 A JP 11900779A JP S5642862 A JPS5642862 A JP S5642862A
Authority
JP
Japan
Prior art keywords
signals
control signal
checking
2aw2f
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11900779A
Other languages
Japanese (ja)
Inventor
Keiichi Hyodo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11900779A priority Critical patent/JPS5642862A/en
Publication of JPS5642862A publication Critical patent/JPS5642862A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the error of the control signal, by giving a checking to the control signal based on the interface rule.
CONSTITUTION: In case the two units are units are controlled by the signal lines AWD of the control signal, the signals shown by the symbols 2W10 are significant in terms of the interface rule. While the states shown by 2AW2F are defined insignificant in terms of the interface rule. Thus the signals are not those which are generated in the normal state. Accordingly, the error of the control signal can be prevented by giving a checking to the generation of the signals 2AW2F. In this connection, the inverters N1WN9 are combined with the gates 3AW3F to form the checking circuit, and the signals of the signal lines AWD are supplied to the checking circuit. As a result, the output is produced from the gate OP when the signals 2AW2F are produced. Through such checking, the error of the control signal can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP11900779A 1979-09-17 1979-09-17 Fault detecting system for electronic computer Pending JPS5642862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11900779A JPS5642862A (en) 1979-09-17 1979-09-17 Fault detecting system for electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11900779A JPS5642862A (en) 1979-09-17 1979-09-17 Fault detecting system for electronic computer

Publications (1)

Publication Number Publication Date
JPS5642862A true JPS5642862A (en) 1981-04-21

Family

ID=14750679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11900779A Pending JPS5642862A (en) 1979-09-17 1979-09-17 Fault detecting system for electronic computer

Country Status (1)

Country Link
JP (1) JPS5642862A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01133645U (en) * 1988-02-29 1989-09-12

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01133645U (en) * 1988-02-29 1989-09-12

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