JPS5614336A - Input switch malfunction preventing circuit - Google Patents

Input switch malfunction preventing circuit

Info

Publication number
JPS5614336A
JPS5614336A JP8960479A JP8960479A JPS5614336A JP S5614336 A JPS5614336 A JP S5614336A JP 8960479 A JP8960479 A JP 8960479A JP 8960479 A JP8960479 A JP 8960479A JP S5614336 A JPS5614336 A JP S5614336A
Authority
JP
Japan
Prior art keywords
malfunction
switch
rom
dependent
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8960479A
Other languages
Japanese (ja)
Inventor
Shinichi Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8960479A priority Critical patent/JPS5614336A/en
Publication of JPS5614336A publication Critical patent/JPS5614336A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To prevent generation of interruption dependent upon a malfunction, by writing an inputtable switch pattern into a ROM previously and by adding the gate circuit, which is controlled by this ROM, to the interruption generating circuit.
CONSTITUTION: The next inputtable switch pattern is written at the address designated by address inputs A0, A1 and A2 of ROM 8 so that this switch pattern may be expressed by outputs P0, P1 and P2 if this address is used as the preceding switch input pattern. Gate circuits 9...11 are controlled by the output of ROM8 to output the switch input dependent upon the normal operation. Meanwhile, gate circuits 12...14 are controlled by the output of ROM 8 to cause the switch input dependent upon a malfunction to pass through. When switch 1 is turned on due to the malfunction, the input signal passes through circuit 12 and is input to FF 16 through OR circuit 15 to display the malfunction on 17 with luminescence. As a result, generation of interruption dependent upon the malfunction can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP8960479A 1979-07-13 1979-07-13 Input switch malfunction preventing circuit Pending JPS5614336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8960479A JPS5614336A (en) 1979-07-13 1979-07-13 Input switch malfunction preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8960479A JPS5614336A (en) 1979-07-13 1979-07-13 Input switch malfunction preventing circuit

Publications (1)

Publication Number Publication Date
JPS5614336A true JPS5614336A (en) 1981-02-12

Family

ID=13975355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8960479A Pending JPS5614336A (en) 1979-07-13 1979-07-13 Input switch malfunction preventing circuit

Country Status (1)

Country Link
JP (1) JPS5614336A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581182A (en) * 1985-02-21 1986-04-08 Air-O-Lator Corporation Submersible mixer with air injection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581182A (en) * 1985-02-21 1986-04-08 Air-O-Lator Corporation Submersible mixer with air injection

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