JPS55124849A - Error detection control system - Google Patents

Error detection control system

Info

Publication number
JPS55124849A
JPS55124849A JP3254879A JP3254879A JPS55124849A JP S55124849 A JPS55124849 A JP S55124849A JP 3254879 A JP3254879 A JP 3254879A JP 3254879 A JP3254879 A JP 3254879A JP S55124849 A JPS55124849 A JP S55124849A
Authority
JP
Japan
Prior art keywords
output
error detection
circuit
constitution
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3254879A
Other languages
Japanese (ja)
Inventor
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3254879A priority Critical patent/JPS55124849A/en
Publication of JPS55124849A publication Critical patent/JPS55124849A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable error detection with a simle constitution, by giving the same input to the same logic circuit and viewing the result of output.
CONSTITUTION: The logic circuits 1, 2 are of the same constitution, and the same input signal is given. The error detection circuit 3 detects whether or not the error is present in the output of the logic circuit 1. The error detection circuit 4 detects whether or not the error is present in the output of the logic circuit 2. Error detection is made, for example, by parity check. The comparison circuit 5 detects the agreement of the output of logic circuits 1, 2. Various states can be judged from the combination of the output signals EP0, EP1, NE of the error detection circuits 3, 4 and comparison circuit 5. The output selection 6 selects normal output signal according to failure and performs output.
COPYRIGHT: (C)1980,JPO&Japio
JP3254879A 1979-03-20 1979-03-20 Error detection control system Pending JPS55124849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3254879A JPS55124849A (en) 1979-03-20 1979-03-20 Error detection control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3254879A JPS55124849A (en) 1979-03-20 1979-03-20 Error detection control system

Publications (1)

Publication Number Publication Date
JPS55124849A true JPS55124849A (en) 1980-09-26

Family

ID=12361978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3254879A Pending JPS55124849A (en) 1979-03-20 1979-03-20 Error detection control system

Country Status (1)

Country Link
JP (1) JPS55124849A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137054A (en) * 1981-10-01 1983-08-15 ストレイタス・コンピユ−タ・インコ−ポレイテツド Highly reliable digital data processor
JP2013106056A (en) * 2011-11-10 2013-05-30 Hitachi Ltd Device with self-diagnostic function

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137054A (en) * 1981-10-01 1983-08-15 ストレイタス・コンピユ−タ・インコ−ポレイテツド Highly reliable digital data processor
JPH0531173B2 (en) * 1981-10-01 1993-05-11 Sutoreitasu Konpyuuta Inc
JP2013106056A (en) * 2011-11-10 2013-05-30 Hitachi Ltd Device with self-diagnostic function

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