JPS54130822A - Line concentrator of analogue line - Google Patents

Line concentrator of analogue line

Info

Publication number
JPS54130822A
JPS54130822A JP3863078A JP3863078A JPS54130822A JP S54130822 A JPS54130822 A JP S54130822A JP 3863078 A JP3863078 A JP 3863078A JP 3863078 A JP3863078 A JP 3863078A JP S54130822 A JPS54130822 A JP S54130822A
Authority
JP
Japan
Prior art keywords
circuits
input
output
circuit
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3863078A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3863078A priority Critical patent/JPS54130822A/en
Publication of JPS54130822A publication Critical patent/JPS54130822A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/17—Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • H04J3/177—Freeze-out systems, e.g. taking away active sources from transmission

Abstract

PURPOSE:To improve S/N of output signals by providing a circuit, which detects whether analogue signals over a fixed level are present or not, and a means, which causes the most preceding output of the input circuit to pass and inhibits other outputs when one or more detector circuits above have detection outputs, for every input line. CONSTITUTION:Input circuits I1 to In are connected to branch circuits H respectively, and one output of branch circuits H is connected to gate circuits G respectively, and the other output of branch circuits H is respectively connected to detector circuits D which are provided in control circuit CONT and detect whether analogue signals over a fixed level are present in the input or not. Outputs of detector circuits D are combined through logical operation circuit L in the control input of gate circuits G. The NAND gate and the FF which are provided in logical operation circuit L of this constitution control to cause only the most preceding output of input circuits I1 to In to pass through gate circuits G from detector circuits D and inhibit other outputs from passing through, and output signals are outputted through synthesizing circuit M to output terminal O.
JP3863078A 1978-03-31 1978-03-31 Line concentrator of analogue line Pending JPS54130822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3863078A JPS54130822A (en) 1978-03-31 1978-03-31 Line concentrator of analogue line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3863078A JPS54130822A (en) 1978-03-31 1978-03-31 Line concentrator of analogue line

Publications (1)

Publication Number Publication Date
JPS54130822A true JPS54130822A (en) 1979-10-11

Family

ID=12530550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3863078A Pending JPS54130822A (en) 1978-03-31 1978-03-31 Line concentrator of analogue line

Country Status (1)

Country Link
JP (1) JPS54130822A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500159A (en) * 1982-03-05 1984-01-26 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Multipoint data communication system for collision detection
JPH0469461B2 (en) * 1982-03-05 1992-11-06 Ei Teii Ando Teii Tekunorojiizu Inc

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500159A (en) * 1982-03-05 1984-01-26 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Multipoint data communication system for collision detection
JPH0469461B2 (en) * 1982-03-05 1992-11-06 Ei Teii Ando Teii Tekunorojiizu Inc
JPH0471376B2 (en) * 1982-03-05 1992-11-13 Ei Teii Ando Teii Tekunorojiizu Inc

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