JPS54130821A - Line concentrator of analogue line - Google Patents
Line concentrator of analogue lineInfo
- Publication number
- JPS54130821A JPS54130821A JP3862978A JP3862978A JPS54130821A JP S54130821 A JPS54130821 A JP S54130821A JP 3862978 A JP3862978 A JP 3862978A JP 3862978 A JP3862978 A JP 3862978A JP S54130821 A JPS54130821 A JP S54130821A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- output
- circuit
- input
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/17—Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To prevent S/N of output signals from deteriorating more than S/N of each input circuit by providing a circuit which detects whether analogue signals are present or not and a gate circuit which controls each input circuit on a basis of the detection result of the circuit above and combining the output of gate circuits. CONSTITUTION:Input lines I1 to In are connected to branch circuits H, and one output of branch circuits H is connected to gate circuits G respectively, and the other is connected to detector circuits D which detect whether analogue signals over a fixed level are present or not. The output of detector circuits D is connected to gate circuits G, and input signals of gate circuits G are connected or disconnected by the output of detector circuits D. Then, respective outputs of gate circuits G are inputted to synthesizing circuit C, and all input signals are combined and outputted at one output terminal O. By this constitution, noise of input circuits where analogue signals over a fixed level are absent is eliminated, and S/N of combined output signals can be improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862978A JPS54130821A (en) | 1978-03-31 | 1978-03-31 | Line concentrator of analogue line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862978A JPS54130821A (en) | 1978-03-31 | 1978-03-31 | Line concentrator of analogue line |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54130821A true JPS54130821A (en) | 1979-10-11 |
Family
ID=12530524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3862978A Pending JPS54130821A (en) | 1978-03-31 | 1978-03-31 | Line concentrator of analogue line |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54130821A (en) |
-
1978
- 1978-03-31 JP JP3862978A patent/JPS54130821A/en active Pending
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