JPS5528525A - Input bias control system for charge transfer element - Google Patents

Input bias control system for charge transfer element

Info

Publication number
JPS5528525A
JPS5528525A JP10040778A JP10040778A JPS5528525A JP S5528525 A JPS5528525 A JP S5528525A JP 10040778 A JP10040778 A JP 10040778A JP 10040778 A JP10040778 A JP 10040778A JP S5528525 A JPS5528525 A JP S5528525A
Authority
JP
Japan
Prior art keywords
signal
bias
input
supplied
charge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10040778A
Other languages
Japanese (ja)
Other versions
JPS5726427B2 (en
Inventor
Kenro Sakagami
Yasoji Suzuki
Tetsuya Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10040778A priority Critical patent/JPS5528525A/en
Publication of JPS5528525A publication Critical patent/JPS5528525A/en
Publication of JPS5726427B2 publication Critical patent/JPS5726427B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To secure an automatic input bias control by giving an automatic detection to the optimum DC bias to the analog signal to be supplied and then biasing the detected DC bias to the analog signal.
CONSTITUTION: The analog input signal is supplied to bias circuit 2 with application of the proper DC bias and then supplied to charge transfer element 3 in the form of the signal charge. The supplied charge is transferred by element 3 and then separated into two systems at branch parts 4 and 5. The signal charge of part 4 is detected as the output signal at circuit 6 and through terminal 7. While the signal charg of part 5 is compared with the reference level at comparator 6. This comparison result is converted into the DC signal through DC converter circuit 9 and then fed negatively back to input bias circuit 2 to be biased by the input signal. Accordingly, if the reference level mentioned above is set previously to secure the optimum input bias level, the optimum bias can always be given automatically to the input analog signal.
COPYRIGHT: (C)1980,JPO&Japio
JP10040778A 1978-08-17 1978-08-17 Input bias control system for charge transfer element Granted JPS5528525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10040778A JPS5528525A (en) 1978-08-17 1978-08-17 Input bias control system for charge transfer element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10040778A JPS5528525A (en) 1978-08-17 1978-08-17 Input bias control system for charge transfer element

Publications (2)

Publication Number Publication Date
JPS5528525A true JPS5528525A (en) 1980-02-29
JPS5726427B2 JPS5726427B2 (en) 1982-06-04

Family

ID=14273114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10040778A Granted JPS5528525A (en) 1978-08-17 1978-08-17 Input bias control system for charge transfer element

Country Status (1)

Country Link
JP (1) JPS5528525A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58132427U (en) * 1982-03-02 1983-09-07 クラリオン株式会社 analog signal delay circuit
JPS58216464A (en) * 1982-06-07 1983-12-16 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Output circuit structure for ccd

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114941A (en) * 1974-02-18 1975-09-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114941A (en) * 1974-02-18 1975-09-09

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58132427U (en) * 1982-03-02 1983-09-07 クラリオン株式会社 analog signal delay circuit
JPS58216464A (en) * 1982-06-07 1983-12-16 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Output circuit structure for ccd
JPS6233751B2 (en) * 1982-06-07 1987-07-22 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPS5726427B2 (en) 1982-06-04

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