JPS5447542A - Sequence control check system - Google Patents

Sequence control check system

Info

Publication number
JPS5447542A
JPS5447542A JP11336077A JP11336077A JPS5447542A JP S5447542 A JPS5447542 A JP S5447542A JP 11336077 A JP11336077 A JP 11336077A JP 11336077 A JP11336077 A JP 11336077A JP S5447542 A JPS5447542 A JP S5447542A
Authority
JP
Japan
Prior art keywords
register
address
steal
shunted
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11336077A
Other languages
Japanese (ja)
Inventor
Michihiro Hirai
Masahiko Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11336077A priority Critical patent/JPS5447542A/en
Publication of JPS5447542A publication Critical patent/JPS5447542A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To ensure a simple and assured confirmation of the normalness of the sequence control in the microprogram control of plural steal levels, by providing the control memory address checking register and the fixed pattern detector circuit.
CONSTITUTION: When a steal is given from microprogram routine (μPR) A to B, microorder address X is shunted to shunt register 3. In case a steal is given from μPRB to C and from C to D, microorder address Y and Z are shunted to shunt register 4 and 5 respectively. At the same instant, the contents of address checking register 7 is shifted to register 8. The contents of address register 2 along with the shunt address order are put into NOR circuit 6, and the output is stored in register 7. This action is performed sequentially by the order shunted to register 5, 4 and 3. When all steals are through, fixed pattern detection circuit 9 checks whether the contents of register 7 is turned to the set fixed pattern. And then whether the steal and the return action are normal or not is made sure
COPYRIGHT: (C)1979,JPO&Japio
JP11336077A 1977-09-22 1977-09-22 Sequence control check system Pending JPS5447542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11336077A JPS5447542A (en) 1977-09-22 1977-09-22 Sequence control check system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11336077A JPS5447542A (en) 1977-09-22 1977-09-22 Sequence control check system

Publications (1)

Publication Number Publication Date
JPS5447542A true JPS5447542A (en) 1979-04-14

Family

ID=14610298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11336077A Pending JPS5447542A (en) 1977-09-22 1977-09-22 Sequence control check system

Country Status (1)

Country Link
JP (1) JPS5447542A (en)

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