JPS5734228A - Timing circuit - Google Patents

Abstract

PURPOSE:To detect the error of a timing (TM) signal which does not fit to an operation cycle by comparing a level change detecting signal to detect the change of the TM signal with a check signal for the TM signal at the normal operation. CONSTITUTION:A TM signal 14 corresponding to the operation of a memory device 39 is generated from a TM signal generating circuit 11. A level detecting signal 36 outputted from a level change etecting circuit 32 to detect the level change at the rise and decay time of the signal 14 is sent to a comparator 34. A check signal from an expected value generation circuit 12 is fed to the circuit 34 and compared with the signal 36 in the circuit 34. The signal 15 has the same phase, logic status and pulse width as those of a level detecting signal outputted from the circuit 32 according to the signal 14 generated from the circuit 11 when the device 39 operates normaly. The circuit 34 compares the signal 36 with the signal 15 and, when these signals do not coincide with each other, an error signal 38 is outputted. Thus, a TM signal which does not correspond to the operation cycle of the device 39 is detected as an error.