JPS592295A - Diagnosis system of memory controller - Google Patents

Abstract

PURPOSE:To detect in an on-line state that various types of control signals are securely generated at a memory controller. CONSTITUTION:A main storage timing generation circuit 8 delivers RAS, REF, CAS, WE, RG, RACA, enable signal EN, etc. with a prescribed timing and in accordance with the corresponding access OK style to access a main storage device 2. A main storage timing monitor part 22 functions as a register to store the state of generation of RAS, REF, CAS, WE, RG, RAS, etc. The data stored in the part 22 are read out to a central processor 1 via drivers 25-26 and then compared with a reference pattern prepared by the processor 1 for each type of monitor. Thus the presence or absence of a fault is detected together with the faulty signal and its timing when a faulty is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for diagnosing whether or not a memory control device is operating correctly, and particularly relates to a method for diagnosing whether or not a memory control device is operating accurately. It is designed to perform a diagnosis.

(2) Background of the technology and its problems A data processing device is provided with a memory control device to efficiently control access to a main storage device. In this case, if this memory control device is not operating accurately, the main storage device cannot be accurately controlled, which may cause a failure. However, there are various types of operating functions in a memory control device, and the control signals for each are complex, and the relative timing relationship of each control signal is a problem. Despite the demand, there was no suitable way to do this.

However, at the time of shipment, we check the timing relationship of each control signal using a synchroscope, etc., and during actual operation, we bring the system online in the event of a failure, monitor the signal timing from the outside, and manually identify abnormalities (C). Therefore, even if an abnormality occurs in the memory control device, it cannot be detected immediately and is detected only after accessing the main memory, so the abnormality detection may be delayed and the cause of the abnormality must be fully investigated. There was a problem that it took a long time.

(3) Object of the Invention An object of the present invention is to provide a memory control device diagnostic method that can detect on-line whether various control signals in the memory control device are accurately generated, in order to improve the above-mentioned problems. It is to provide.

(4) Structure of the Invention In order to achieve this object, the memory control device diagnostic method of the present invention provides a data processing device that includes a processor, a storage device, and a memory control device that controls the storage device.
A sampling data holding means is provided for sampling the control signal sent from the memory control device to the storage device and holding the sampling result, and the memory control device normally uses the sampling data held by the sampling data holding means. It is characterized by being able to compare and check with reference data during operation to determine whether or not it is operating normally, and to detect abnormal locations online.

(5) Embodiment of the Invention Before explaining the present invention in detail based on one embodiment, its operating principle will be briefly explained based on FIG. 3.

Among the memory control signals output from the memory control device to the main storage device, M essential ones are called RAS timing signals (hereinafter referred to as RA
(referred to as S)1. CAS timing signal (hereinafter referred to as CAS), R/W enable signal (hereinafter referred to as WE), memory read gate signal (hereinafter referred to as RG), memory address switching timing signal (hereinafter referred to as RACA)
and a refresh signal (hereinafter referred to as REF). In the operand store operation (p-s), RAS, CAS, and WE are executed at the timing indicated by BS in FIG.

Four types of RACA signals are output, and in the case of instruction 7-process operation or operand 7-process operation (P-F), RAS is output at the j timing shown in P-F in FIG.

Four types of signals, CAS, RG, and RACA, are output, and in the case of a refresh signal (RF), two types of signals, RAS and REF, are output at the timing shown as RF in FIG. Therefore, each signal generation pattern during normal operation at sample times T1 to T4 is held as a 6-pit binary pattern. Then, during diagnosis, the operating state of the memory control device is diagnosed by detecting the output pattern of each of these signals at sampling Φ times T1 to T4 and comparing these with normal patterns held in advance according to the operation type. can do.

A #J hook of the present invention will be explained based on FIGS. 1 to 3.

FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of the main part thereof, and FIG. 3 is an explanatory diagram of the operation.

In the figure, 1 is a central processing unit, 2 is a main storage device, 3 is a memory control device, 4 is a timing monitor, 5 is an inverter, and 6
is a memory control memory, 7 is a main memory access contention circuit,
8 is a main memory timing generation circuit, 9 is a latch, 14 is an OR circuit, 16, 18° 19 is a driver, 20.21 is a driver/resino, (, 22 is a main memory timing monitor section, 23 is a timing control section, 25 .26 is the driver,
27 is an AND circuit.

The central processing unit 1 reads data necessary for data processing from the main storage device 2 and performs calculations, or sends the calculation results to the main storage device 2, as well as standard data and diagnosis, which will be described in detail later. It also performs control to diagnose the operating state of the memory control device 3 based on the dictionary.

The memory control device 3 performs various controls for accessing the main memory device 2 and refresh control for the main memory device 2, and includes a memory control memory 6, a main memory access contention circuit 7, and a main memory shown in FIG. Timing generation circuit 8
etc. are provided.

The timing monitor 4 includes a register shown as a main memory timing monitor section 22 and a timing control section 23, and controls the RAS, REF, CAS, and WE according to the sampling timings T1 to T4 shown in FIG.

It stores the generation states of six types of signals, RG and RACA. This register of the timing monitor 4 stores the generation states of six types of signals during the sampling times T1 to T4.

In the case of an operand store operation (p-s) that stores data in the main memory device 2, the generation states of the six types of signals at sampling times T1 to T4 indicate that the memory control device 3 is operating normally. If you want to use roo
ooooJ, rloololJ.

They will be stored in the timing monitor 4 as rlollolJ and rooloooJ.

The memory control memory 6 outputs a command to control the memory control device 3 in response to a startup command from the central processing unit 1, and is constituted by a ROM.

The main memory access competition circuit 7 determines which one should be prioritized when there are multiple access requests to the main memory 2. 0s7 retrieval request REFRQ
, an access request CHCRQ from the channel control device, various requests transmitted from the central processing unit 1 to the mesoribei system via the memory 6, etc., but when some of these conflict, it is difficult to decide which one to select. This main memory access contention circuit 7 makes a decision based on a predetermined algorithm. When the access request transmitted from the channel control device is selected, the R, EFOK signal is output to the main memory timing generation circuit 8, and when the access request transmitted from the channel control device is selected, the CHCOK signal is output to the main memory timing generation circuit. 8, and the central processing unit empty instruction fetch (I-F), operand 7 fetch (P
-F), operand store (p-s), etc. is selected, a corresponding CCOK multiplied signal is output to the main memory timing generation circuit 8. 1. The main memory timing generation circuit 8 generates the above-mentioned RAS and REF necessary for accessing the main memory device 2.

CAS, WE, RG, RACA, enable signal EN, etc. are output at predetermined timings as shown in FIG. 3 according to the access OK mode.

The main memory timing monitor part 22 has RAS and REF, as explained in the timing monitor 4 above.

This is a register that stores the occurrence status of CAS, WE, RG, RACA, etc., and the stored data is sent to the driver 25.
... is read out to the central processing unit 1 via 26, and compared with a reference pattern for each monitor type separately prepared in the central processing unit 1, and it is checked whether there is an abnormal state and, in the case of an abnormal state, which signal is detected at which timing. It will be detected whether there is an abnormality.

The timing control section 23 has two types of locks shown in FIG.
A sampling clock faster than the phase lock is created, and the six types of signals transmitted to the main memory timing monitor section 22 are sampled using this clock, and the signals are transmitted via the main memory access contention circuit 7. In response to the monitor activation signal, the address and write signal WE are sent to the main memory timing monitor section 22, and the generation state of the signal according to the monitor type is stored. It also has a function of setting the type of instruction at the time of monitoring, and outputs a WE times signal for each monitor type based on the output signals REFOK and CC0K of the main memory access contention circuit 7.In this way, the data of the monitor type is collected. Can be monitored.

In FIG. 2, when accessing the main memory device 2, in the case of a refresh request, the refresh address REF'Ad is transmitted via the driver 16, and in the case of a memory access from the central processing unit 1. The memory address CCMAR written in the address register in the central processing unit is transmitted to the driver 18f via the driver 18f.The memory address CCMAR at this time is also valid during diagnosis. In this case, the memory address CHCMAR written in the address register in the channel control device will be transmitted via the driver 19. In these cases, the main memory @
Read data or write data regarding 2 is transmitted via the bidirectional driver receiver 20 when the access source is a central processing unit, and via the bidirectional driver receiver 21 when the access source is a channel control device. Become something.

Next, a diagnostic operation for the memory control device will be explained. Diagnosis of the memory control device is performed by storing various timings of the six types of memory control signals in a 4-word register of the main memory timing monitor section 22. There are five types of monitors for this memory control device:

Among these, ■■■ is the memory control signal generated in the state shown in P-F in Figure 3, ■ is the same in the state shown in <p-s, and ■ is the same in the state shown in R and -F, respectively. A control signal is generated.

■Instruction 7 Fetch operation (Jump instruction-I-Fetc
h, 'Monitor ■ Instruction fetch operation (next instruction fetch when instruction ends - M
DI-Fetch) monitor ■ Operand fetch operation (P-Fetch) monitor ■ Operand store operation (P5tore) monitor ■ Refresh operation monitor The selection signals for these five types of monitors are output from the central processing unit 1 and are used for memory control. data is transmitted to the memory 6 for use.

(2) When performing this diagnosis, the central processing unit sets a diagnosis designation command to the latch 9, outputs "work"), turns the AND circuit 27 on, and the timing control section 23 starts operating. At this time, in response to the clear signal from the central processing unit, the timing control unit 23 outputs the quadruple rear signal CLE' at the falling edge of the sample clock.
AR'(5 is output and applied via the AND circuit 27 to clear the main memory timing monitor section 22.

@ Specify the monitor type and perform the desired main memory access operation according to the monitor type command from the central processing unit 1 at monitor start'. This is held in the timing control unit 23, and the timing control unit 23 monitors that the operation specified by the monitor type is actually executed by winning the main memory access competition circuit.O θ The specified memory access operation is executed. When the timing control unit 23 receives the generation state of the six types of signals at that time, the write enable signal W activated by the output of the main memory access contention circuit at sample times T1 to T4.
By outputting E, the main memory timing monitor section 22
Have them fill in the information.

O Next, the central processing unit engineer sends the generation states of the six types of signals stored in the main memory timing monitor section 22 and corresponding to the monitor type sequence, together with information representing the monitor type, via the drivers 25 to 26. and read it out.

(2) The central processing unit 1 compares and verifies the read data with reference data during normal operation read out separately from its own reference data holding section, and checks whether or not they match. If they match, it is determined that the operating state of the memory control device is normal, and if they do not match, the abnormality is detected and reported using a diagnostic switch owned according to the mismatched capital stock.

(6) Effects of the Invention According to the present invention, the operational status of the memory control device can be diagnosed online.As a result, abnormalities can be detected quickly, so that, for example, data geography devices can be divided into active and standby systems. When operating at 2M, such as in a dual system, abnormalities can be discovered early and switched to a standby system, thereby reducing damage.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of the main part thereof, and FIG. 3 is an explanatory diagram of the operation. In the diagram, 1 is a central processing unit, 2 is a main memory, 3 is a memory control device, 4 is a timing monitor, 6 is a memory control memory, 7 is a main memory access competition circuit, 8 is a main memory timing generation circuit,
22 is a main memory timing monitor section, and 23 is a timing control section.

Claims (1)

[Claims] (1) In a data processing device that includes a processor, a storage device, and a memory control device that controls the storage device,
A sampling data holding means is provided for sampling the control signal sent from the memory control device to the storage device and holding the sampling result, and the memory control device normally uses the sampling data held by the sampling data holding means. A memory control device diagnostic method 0 characterized in that it compares and checks with reference data during operation to determine whether or not it is operating normally, and also detects abnormal locations online.