JP3317776B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of processors, and more particularly, to enabling an arbitrary combination of a dual processor and a single processor.
Information processing that enables selection of an appropriate combination of performance and reliability
It concerns the device .

[0002]

2. Description of the Related Art Conventionally, in order to improve the reliability of an information processing system, a master processor and a checker processor perform the same operation, and a fault detection is performed by comparing the execution results of the master processor and the checker processor. A processor system has been implemented. For example,
Japanese Patent Application Laid-Open No. Sho 62-160539 discloses that two identical processors are connected to one bus connected to a main storage device, and one is a master processor and the other is a checker processor. Operate at the same time,
A dual processor system that compares both results is described.

On the other hand, in order to improve the performance of an information processing system, a so-called multiprocessor system in which a main storage device is shared by a plurality of processors has been realized. For example, Japanese Patent Application Laid-Open No. 3-196249 discloses a main storage device. A multiprocessor system in which a plurality of processors are connected to one connected bus and each executes an independent program is described.

Further, when both the reliability and the performance of an information processing system are satisfied, conventionally, two sets of a master processor and a checker processor are fixedly set as one set.
It realized a system in which multiple sets of redundant processor systems were made multiprocessors.

[0005]

In a dual processor system, a multiprocessor system, and a combination thereof, in a conventional system, the role of each processor is fixed, and the system is flexibly and economically used. There was a drawback that could not be constructed. That is, 2
In the redundant processor system, the combination of the master processor and the checker processor is fixed, and the point that the two processors execute the same program is fixed even though the roles of the master and the checker can be exchanged. . Therefore, the reliability is improved, but the performance is the same as one processor. Further, in a multiprocessor system, each processor is created so as to always execute an independent program. Even if two processors execute the same program, the same operation is executed at the same time. Since the execution results are checked for consistency and the system operation is not affected, there is no difference from executing an independent program. Therefore, since the two processors operate independently, the performance is improved, but the reliability is not improved.
The system is different from the dual processor system from the beginning. Further, in a duplicated multiprocessor system, the combination of the master processor and the checker processor to be duplicated is fixed, and a set of processors that execute the same program and an independent program if the combination is different are used. Since the assignment of the processors to be executed is fixed, it has been impossible to flexibly change the performance and reliability according to the state of the system, including changes during system operation.

By the way, it can be understood that the dual processor system, the multiprocessor system, and the system based on the combination thereof are surprisingly similar when paying attention to the connection form between the processor and the main storage device. For example, 2
Two processors are coupled to one main storage device
Comparing a duplicated processor system with a multiprocessor system, it is found that each processor executes the same program, compares the results, and increases reliability. Can be said to be a multiprocessor system that has improved the performance. That is, a dual processor system assigns processors coupled to the system to improve reliability, and a multiprocessor system assigns processors to improve performance. Therefore, by enabling these to be freely changed according to the state of the system, it is possible to construct a system with optimum performance and reliability.

Accordingly, an object of the present invention is to make it possible to arbitrarily combine a dual processor and a single processor in an information processing system having a plurality of processors, and to provide a dual processor according to system conditions. A system, a multiprocessor system, and a system in which these are combined can be freely constructed and changed.

[0008]

According to the present invention, an information processing apparatus having two processors is provided with an operation mode indicating that the two processors operate in a multiprocessor mode or a master checker mode. In mode, memory requests alternately to two processors
A multiprocessor system in which the two processors execute independent programs, respectively,
In master checker mode, memory is stored in two processors .
Quests are allowed at the same time, and the two processors constitute a dual processor system that executes the same program as one of a master processor and the other as a checker processor, and these modes can be switched. I do.

Further, according to the present invention, in an information processing apparatus having three or more processors,
A logical processor number and an identification bit for a master mode or a checker mode are provided, and a duplicated processor set having the same logical processor number and having the master mode and the checker mode set, respectively, and a master processor only having no checker processor. Divided into single processor and 2
Memory for each redundant processor and single processor in turn
A multiprocessor system is configured by permitting requests, and combinations of these processors are freely performed.

[0010]

According to the present invention, the logical processor number and / or the identification mode are changed according to the state of the system, thereby arbitrarily constructing a dual processor, a multiprocessor, or a system combining these. This makes it possible to construct an optimal system of performance and reliability for an information processing apparatus having a plurality of processors.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention. In an information processing apparatus in which two processors are connected to a main storage device, according to a multiprocessor / master checker identification mode. A multiprocessor system in which two processors each execute an independent program,
Alternatively, the execution of the same program using one as the master processor and the other as the checker processor enables the configuration of the dual processor system to be freely switched.

In FIG. 1, processor 0 (IP0)
1. Processor 1 (IP1) 2 is connected to a main storage controller (SCU) by independent processor buses 101 and 102, respectively.
3 is connected. SCU busy signals 103 and 104 and failure report signals 105 and 106 are connected between the processors 1 and 2 and the SCU 3. The SCU busy signals 103 and 104 are transmitted by the SCU 3 to the processors 1 and 2.
Indicates that a request from processor 1 cannot be accepted while signal 103 is being output, and that a request from processor 2 is not accepted while signal 104 is being output. Is shown. The failure report signals 105 and 106 are signals for notifying the processors 1 and 2 of the failure detected by the SCU 3.

The SCU 3 has a selector 10 for selecting the processor 0 or 1; an address register 11 for setting a request address from the processor 0 or 1;
A write data register 14 in which write data is set,
Parity checker 15 for checking addresses and write data, comparator 16 for comparing addresses and data of processors 0 and 1 in master checker mode, response register 1 for setting read data from main storage device 4
7, 18; comparison circuits 19, 20 for controlling the operation of the response registers 17, 18 according to the multiprocessor / master checker mode; and AND gates 35, 3
6, the selected processor number (processor 0 is “0”,
A processor number register 21 in which the processor 1 is set to "1", an operation mode register 22 in which the operation modes of the processors 0 and 1 (multiprocessor / master checker mode) are set, and a failure report to the processors 0 and 1 , A multiprocessor / master checker mode, and a processor switching controller 2 that controls processor switching according to read / write
4 and amplifier gate groups 51-57. In addition,
107 is a reception switching signal, 108 and 109 are response processor number signals, 110 is an operation mode switching signal, 11
Reference numeral 1 denotes a selected request signal line.

The operation of the two processors in FIG.
3 is determined by the operation mode register 22. In FIG.
4 shows a configuration example of an operation mode register 22. The operation mode register 22 is composed of two bits, and the processor 0 has three types of modes: a master checker mode of the master processor, a processor 1 a master checker mode of the master processor, and a multiprocessor mode in which the processors 0 and 1 operate independently. Mode (“00”, “01”, “1”
X ") is set. The setting of the operation mode in the operation mode register 22 will be described later.

The contents (operation mode) of the operation mode register 22 are sent to the processor switching control unit 24, and from there, a desired reception switching signal 107, response processor number signals 108 and 109, and SCU busy signals 103 and 104 are output.
Is output. FIG. 3 shows an operation diagram of the processor switching control unit 24, and FIG. 4 shows an example of the internal logical configuration thereof.

In FIG. 4, the operation mode switching logic unit 13
Is for rewriting the operation mode register 22 through the signal line 110 when a mode switching request is issued from the processor. The decoder 26 sets the outputs a and b to 0 when the contents of the operation mode register 22 are “00”, sets the output a only to 1 when the contents are “01”, and sets the output b only to 1 when the contents are “1X”. The write detection logic unit 27 sets the output to 1 when a write request is detected, and sets the output to 0 otherwise. The selection signal register 25 is a register in which the value of the selected processor number is stored for each cycle. When the operation mode is the master checker mode, the register 25 indicates the master processor number at that time irrespective of the value of the previous cycle. In the multiprocessor mode, the processor number is changed every cycle except for the write instruction. The processor number is switched in two cycles in the write instruction. Selection number register 25
The above operation is controlled by the OR gate 28, AND gates 31, 32, and note gates 47, 48. The reception switching signal 107 is output from the OR gate 29 and the AND gate 333.
Indicates the value of the master processor number at that time in the master checker mode, and indicates the value of the selection signal register 25 in the multiprocessor mode. The SCU busy signals 103 and 104 show contradictory values in the multiprocessor mode by the AND gates 34 and 46, respectively. The response processor number signal 108 indicates the master processor number in the master checker mode, and always indicates the processor number 0 in the multiprocessor mode. The response processor number signal 109 is
Indicates the master processor number in the master checker mode, but always indicates the processor number 1 in the multiprocessor mode.

FIG. 5 shows an example of the internal logical configuration of the fault report control unit 23. Here, the decoder 37 determines the content (operation mode) of the operation mode register 22, and sets the output to 1 in the multiprocessor mode (“1X”). In the master checker mode, the comparator 16 detects an operation mismatch between the master processor and the checker processor, and / or
When the parity checker 15 detects a parity error,
Both the failure report signals 105 and 106 indicate that a failure has occurred. In the multiprocessor mode, when the parity checker 15 detects a parity error, the failure report signals 105 and 10 are output.
6, the one corresponding to the processor being accepted in that cycle indicates that a failure has occurred. The failure report signals 105 and 10
Controlling the state of No. 6 is the NOT gates 38 and 39, the AND gates 40 to 43, and the OR gates 44 and 45.

Next, the operation of FIG. 1 will be described with reference to FIGS. When the processor 0 is in the master checker mode of the master processor (operation mode: 00), the reception switching signal 107 is always “0” and the response processor number 10
8 and 109 are both "0" (FIGS. 3 and 4). At this time, in the main memory read operation, the request address sent from the processor 0 as the master processor is selected by the selector 10 and set in the address register 11,
The parity number is checked by the parity checker 15. At the same time, the processor number "0" is set in the processor number register 21. The processor number register 21 is compared with the response processor numbers 108 and 109 by the comparators 19 and 20. In the master checker mode, since these comparison results are always "1", the AND gates 35 and 36 are both conductive. . Therefore, the read data read from the main storage device 4 at the address of the address register 11 passes through the AND gates 35 and 36 to the response register 1
7 and 18 are set, and the processor buses 101 and 1 are set.
The data is sent to both the processors 0 and 1 via 02. On the other hand, the request address sent from the processor 1 which is the checker processor is
Are compared with each other, and if they do not match, the failure report control unit 23 is notified. In the failure check control unit 23, in the master checker mode, the comparator 16 and the parity checker 15
Is always sent to both processors 0 and 1 (FIG. 5). At the time of the main memory write operation, the request address and the write data sent from the processor 0 as the master processor are selected by the selector 10 and set in the address register 11 and the write data register 14. Since no response is required during the write operation, setting of the processor number register 21 is unnecessary. The write data of the write data register 14 is written into the main storage device 4 at the address indicated by the address register 11. The request from the processor 1 which is a checker processor is compared with the address and the data by the comparator 16 respectively, and when a mismatch is detected, both are notified to the processors 0 and 1 through the fault report control unit 23. Also, the parity checker 15
Is the address of processor 0, the master processor,
When both data are checked and a failure is detected, both processors are similarly notified via the failure report control unit 23.

When the processor 1 is in the master checker mode of the master processor (operation mode: 01), the reception switching signal 107 is always "1" and the response processor number 10
8 and 109 are both "1" (FIGS. 3 and 4). The operation at this time is as follows, except that the address and data selected by the selector 10 always select from the processor 1.
This is the same as when the processor 0 is in the master checker mode of the master processor. Naturally, the processor number "1" is set in the processor number register 21, but the response processor numbers 108 and 109 also indicate "1", so that the comparison results of the comparators 19 and 20 are always "1".
In the main memory read operation, data read from the main memory 4 is set in both the response registers 17 and 18 and sent to both processors via the processor buses 101 and 102.

When the operation mode register 22 is in the multiprocessor mode (operation mode: 1X), the processors 0 and 1
Are different from each other, the processor switching control unit 24 controls which request is accepted. The value of the selection number register 25 in FIG. 4 is normally (every other than the write operation) switched every cycle through the path of the knot gate 47, the AND gate 32, and the OR gate 28, and this is the reception switching signal 107 by the AND gate 33 and the OR gate 29. Is reflected in the selector 1
0 alternately selects the requests of the processors 0 and 1 every cycle. On the other hand, when the received request is a write request, it is necessary to receive write data together with the address. Therefore, in the processor switching control unit 24, the AND gate 32 is suppressed by the write detection logic unit 27.
By making the AND gate 31 conductive, the value of the selection number register 25 is extended by one cycle. In this multiprocessor mode, the SCU busy signals 103 and 10 are set to indicate that no request has been accepted for a processor not selected by the selection number register 25.
4, a knot gate 47, an AND gate 34,
The SCU busy signal 104 is output to the processor 1 while the selection number register 25 is selecting the processor 0, and the SCU busy signal 103 is output to the processor 0 while the selection number register 25 is selecting the processor 1. That is, the SCU busy signals 103 and 104 are alternately output in synchronization with the reception switching signal 107.

FIG. 6 shows an operation time chart in the multiprocessor mode of FIG. In FIG. 6, in the cycles (1) to (5), there is no request from any of the processors 0 and 1, and the SCU busy signal 10 is simply synchronized with the reception switching number 107, that is, the selection signal register 25.
3, 104 are output alternately. In the multiprocessor mode, the response processor numbers 108 and 109 always output "0" and 109 output "1" (FIGS. 3 and 4).

Cycles (6) to (9) in FIG. 6 show the main memory read operation in the multiprocessor mode. Processor 0 and processor 1 cycle (6)
In this cycle, the selector 10 selects the processor 0 request address because the selection number register 25 has selected the processor 0 in this cycle, and this address is set in the address register 11. At the same time, the processor number “0” which is the value of the reception switching signal 107 is set in the processor number register 21. The contents of these registers 11 and 21 are determined at the beginning of cycle (7). In this way,
In the cycle (7), the processor number register 21 is "0", the comparator 19 is "1", the comparator 20 is "0", the AND gate 35 is conductive, and the AND gate 36 is disabled. . Therefore, the read data read from the main storage device 4 in the cycle (7) passes through the AND gate 35 and the response register 17
, Which is determined at the beginning of cycle (8) and sent to processor 0 in cycle (8). On the other hand, the request from the processor 1 which has been waiting in the cycle (6) due to the output of the SCU busy signal 104 is accepted by the selection number register 25 selecting the processor 1 in the cycle (7) and passed through the selector 10. Is set in the address register 11. Further, “1” is set in the processor number register 21. In the cycle (8), the processor number register 21 is "1", the comparator 19 is "0", the comparator 20 is "1", the AND gate 35 is in the inhibited state, and the AND gate 36 is in the conductive state. . Therefore, the read data read from the main storage device 4 in cycle (8) is set only in the response register 18 through the AND gate 36, and is sent to the processor 1 in cycle (9).

The cycles (12) to (16) in FIG.
This shows the main memory write operation in the multiprocessor mode. When the processor 0 and the processor 1 simultaneously generate a write request in the cycle (12), the selector 10 selects the request address of the processor 0 in this cycle because the selection number register 25 selects the processor 0, and this address is It is set in the address register 11 and is determined at the beginning of the cycle (13). As in the master checker mode, no response is required when writing to the main memory, so that setting of the processor number register 21 is unnecessary. As described above, at the time of a write request, the same value is held in the selection number register 25 for another cycle, so that the write data of the processor 0 is set in the data register 14 in cycle (13).
This is determined at the beginning of cycle (14). Thus, the data is written to the main storage device 4 in the cycle (14). On the other hand, the request from the processor 1 is waited in cycles (12) and (13), accepted in cycle (14), the selector 10 selects the request address of the processor 1, and the selected address register 1
1 is set, and is determined at the beginning of cycle (15). Subsequently, the write data selected in cycle (15) is set in the write data register 14, and in cycle (1)
At the beginning of 6), the data is written to the main storage device 4 in cycle (16) in order to be determined.

As for the fault in the multiprocessor mode, the master checker mismatch fault using the comparator 16 is always suppressed, and only the output of the parity checker 15 is sent to the processor selected by the reception switching signal 107 (FIG. 5). . That is, the failure detected when the reception switching signal 107 is “0” is notified to the processor 0 by the failure report signal 105 via the AND gate 42 in the failure report control unit 23. Further, the fault detected when the reception switching signal 107 is “1” is notified to the processor 1 by the fault report signal 106 via the AND gate 43 in the fault report control unit 23.

The mode setting of the operation mode register 22 shown in FIG. 1 can be realized by performing the same operation as the ordinary hardware register write. For example, it can be realized by assigning a specific address of a request from the processor to a hardware register of the main storage control device and issuing a write request to these. In this embodiment, as shown in FIG. 4, the operation mode switching detection logic unit 13 is provided in the processor switching control unit 24, and when a mode switching request is issued from the processor and output to the request signal line 111 after selection. Detecting this, fetching the mode data (a kind of write data), the operation mode switching signal 110
Is output, and the operation mode register 22 is rewritten. The operation mode switching detection logic unit 13 is realized by a decoder that separates a request type from a request from a processor, similarly to the write detection logic unit 27.

The change from the master checker operation to the multiprocessor operation is realized by rewriting the operation mode register 22 by the master processor. The master processor executes the processing as it is, but the checker processor operates independently of the instruction following the operation mode register write. After the switching, each processor recognizes its own processor number and executes an independent program.

The change from the multiprocessor operation to the master checker operation is realized by the processor which will become the master processor in the future rewriting the operation mode register 22. After changing the operation mode, the master processor saves all information in the processor, such as general-purpose registers, floating-point registers, program counters, and control registers, once to the main storage device, and issues a reset to both the master processor and the checker processor, Thereafter, by recovering the information in the processor saved in the main storage device to both processors, the master checker processor is synchronized and operates as a duplex processor.

FIG. 7 is an overall block diagram of a second embodiment of the present invention. In an information processing system in which four processors are connected to a main storage device, each processor has a logical processor number and a master mode or checker. By setting the mode, a multiprocessor system including a set of duplicated processors having the same logical processor number and being set to the master mode and the checker mode, respectively, and a single processor having only the master processor without the checker processor is provided. Thus, the combination of these processors can be freely switched.

In FIG. 7, processor 0 (IP0) 2
00, processor 1 (IP1) 201, processor 2
(IP2) 202 and processor 3 (IP3) 203
Independent processor buses 250 to 253 are connected to the main storage controller (SCU) 204. In addition, between each processor 200 to 203 and the SCU 204, an individual SCU busy signal 254 to 257
Further, a common failure report signal 267 is connected to each processor.

The SCU 204 includes a selector 206 for selecting one of the processors 0 to 3 according to the reception switching signal 264, an address register 207 for setting a request address of the selected processor, and a write data for setting write data of the selected processor. A register 208, a processor number register 209 in which a selected processor number (logical processor number) is set, response registers 210 to 213 corresponding to processors 0 to 3 in which read data from the main storage device 205 are set, and each response register 2
AND gate 21 for controlling operations of 10 to 213
4-217, comparison circuits 220-223, processor 0
Operation mode register 23 in which the operation modes of .about.3 are set
0, a processor switching controller 231 for controlling switching of processors 0 to 3, a selection number register 232 in which a processor number (logical processor number) selected in each cycle is set, a write detection logic unit 233 for detecting a write request, An operation mode switching logic unit 234 that switches the operation mode of the register 230, a request address, write data consistency (a set of master checkers), a failure report control unit 266 that detects an error and reports it to the processors 0 to 3, and , And application gate groups 240 to 249. Note that 260 to 263 are response processor number signals, 264 is a reception switching signal, and 265 is a selection number register input signal.

The operation of the four processors in FIG.
The operation mode is determined by the operation mode register 230 in the memory 204. The operation mode register 230 has a total of 12 as shown in FIG.
The first two bits indicate the logical processor number, and the last one bit indicates the master checker identification mode. Here, the logical processor number is a number that is virtually assigned separately to a processor number unique to the processor. The logical processor number is variable, and in this embodiment, “00” (logical processor number 0), “01” according to the operation mode of the four processors 0 to 3.
(Logical processor number 1), "10" (logical processor number 2), or "11" (logical processor number 3). The latter one bit is “0” when the processor is a master processor and “1” when the processor is a checker processor.

The contents (operation mode) of the operation mode register 230 are sent to the processor switching control section 231 and the processor switching control section 231 causes the selection number register 23
2. Reception switching signal 264, SCU busy signal 254-2
57, the response processor number signals 260 to 263 are controlled. FIG. 9 shows an operation diagram of the processor switching control unit 231 for four types of operation modes as an example. Here, the basic operation is the same as that of FIG. 3 except that the selection number register 232, the reception switching signal 264, and the response processors 260 to 263 are indicated by logical processor numbers. Note that an internal logic diagram of the processor switching control unit 231 is omitted.

In FIG. 9, the first is a four-processor multiprocessor mode in which processors 0 to 3 are assigned to logical processor numbers 0 to 3, respectively, and operate on independent master processors. Second, processor 0 is assigned to the master processor of logical processor number 0, processor 1 is assigned to the checker processor of the same logical processor number 0, processor 2 is assigned to the master processor of logical processor number 1, and processor 3 is assigned to the master processor of logical processor number 2 And a three-unit multiprocessor mode with one set of master checker configuration and two single processors. Third, processor 0 is the master processor of logical processor number 0, processor 1 is the checker processor of logical processor number 0, processor 2 is the master processor of logical processor number 1, and processor 3
Are assigned to the checker processor of the same logical processor number 1 and are in a two-unit multiprocessor mode with two sets of master checkers. Fourth, in the second case, with respect to a set of processors 0 and 1 in the master checker configuration of logical processor number 0, a failure occurs in processor 0 as a master processor, and processor 1 becomes the master processor and processor 0 becomes the This is the case when switching to the checker processor is performed. Hereinafter, the operation of FIG. 7 will be described using these operation modes as examples. The operation mode register 230 can realize various operation modes other than the above. However, since it can be easily inferred from these modes, the description is omitted here.

In the first four-unit multiprocessor mode, the selection number register 232 stores the logical processor number 0.
, 1, 2, and 3 are sequentially selected for each cycle. Other than the selected processor, the SCU busy signal becomes "1", and requests from these are suppressed. For example, when logical processor number 0 is selected, processors 1 to 3
SCU busy signals 255 to 257 become “1”, and only the request from processor 0 is accepted. When the processor 0 issues a read request, the request address from the processor 0 is stored in the selector 206.
Is set in the address register 207, and the processor number register 209 simultaneously stores the logical processor number 0
Is set. The processor number register 209 stores the response processor number signals 260 to 263 and the comparator 220
２223, and only the comparator 220 outputs a coincidence signal, so that the AND gate 214 is conductive and the other AND gates 215 to 217 are nonconductive. As a result, the address of the main memory 2
The read data read from 05 is AND gate 2
14 and set in the response register 210 and sent to the processor 0. When processor 0 issues a write request, the request address and write data sent from processor 0 are selected by selector 206, and address register 207 and write data register 2
08 is set. Since no response is required during the write operation, setting of the processor number register 209 is unnecessary. In a write operation, the write detection logic unit 233 recognizes that a write operation is performed in the request address cycle with the same logic as that described with reference to FIGS. By choosing the same processor as the cycle,
Fetch request data. In the main storage device 205,
The write data of the write data register 208 is written to the address indicated by the address register 207. Even when the selection number register 232 selects the logical processor numbers 1, 2, and 3, it can operate by accepting only the request of the selected processor in the same manner as described above.

In the second three-processor multiprocessor mode, the selection number register 232 stores the logical processor number 0.
And 1 and 2 are selected in turn. In this case, the processors of the master checker configuration perform the same operation because the master and the checker have the same logical processor number. In this example, when the logical processor number 0 is selected, the SCU busy signals 254 and 255 of the processors 0 and 1 are “0”,
257 of the SCU busy signal 256 of the processors 2 and 3 becomes “1”, and only the requests of the processors 0 and 1 are accepted. Read requests and write requests from all master processors operate in response to requests from the processor selected by the selection number register 232, as in the case of the first four multiprocessors. Since the checker processor operates simultaneously with the corresponding master processor having the same concluded processor number, the issuance of a normal read request or write request is the same as that of the master processor (here, processors 0 and 1).
However, the request from the checker processor is not selected by the selector 206, and is output by the failure report control unit 266.
The request is compared with the request from the corresponding master processor.
0 to 203 are notified. The response data is transmitted to the checker processor at the same time as the response data of the synchronized master processor. That is, in this example, since both the response processor numbers 260 and 261 are “0”, both the comparators 220 and 221 are established, and
The same content is sent to both processors.

In the third multiprocessor mode, the operation is substantially the same as that in the second multiprocessor mode. However, the selection number register 232 alternately selects the logical processor numbers 0 and 1. For example, when the logical processor number 0 is selected, the SCU busy signals 254 and 255 of the processors 0 and 1 become “0”, the SCU busy signals 256 and −257 of the processors 2 and 3 become “1”, and the request of the processors 0 and 1 becomes Only processor 0 operates as a master processor and processor 1 operates as a checker processor. Similarly, when the logical processor number 1 is selected, the SCU busy signals 256 and 257 of the processors 2 and 3 are set to “0”, and the SCU of the processors 0 and 1 are set to “0”.
The busy signals 254 and 255 become "1", and only the requests from the processors 2 and 3 are accepted. The failure report is compared by the failure report control unit 266 with the request of the master processor and the request of the check processor corresponding to the same logical processor number.
At 7, each processor is notified.

The operation in the fourth three-processor multiprocessor mode is exactly the same as the second operation in the second case, except that the processor 1 is replaced by a master processor and the processor 0 is replaced by a checker processor.

In FIG. 7, the operation mode register 230
The setting of the mode can be realized by the operation mode switching logic unit 234, similarly to the operation mode switching logic unit 13 of FIG. That is, a specific address of a request from the processor is assigned to a hardware register (operation mode register 230) of the main memory control device. When a write request is issued here, the operation mode switching detection logic 234 detects the write request. ,
The operation mode register 230 is rewritten.

Switching from the first operation mode to the second operation mode is as follows.
Processor 0, which will become a master processor having a master checker configuration in the future, rewrites the operation mode register 230 to a new operation mode. After changing the operation mode, the processor 0
All information in the processor, such as general-purpose registers, floating-point registers, program counters, and control registers, is once saved in the main memory, a reset is issued to both processors 0 and 1, and then the information in the processor saved in the main memory is saved. By recovering information to both processors, the master checker processor is synchronized and operates as a duplex processor. The processors 2 and 3 operate in the same manner as before the mode change except that the logical processor number changes.

Similarly, when the operation mode is switched from the second operation mode to the third operation mode, the processor 2 rewrites the operation mode register 230, and after changing the operation mode, the processor 2 sets the general-purpose register, the floating-point register, the program counter, the control register, etc. All the information in the processor is once saved in the main storage device, a reset is issued to both the processors 2 and 3, and the information in the processor saved in the main storage device is then restored to both processors, thereby obtaining the master checker. The processors synchronize and operate as a duplex processor.

Switching from the third operation mode to the second operation mode and switching from the second operation mode to the first operation mode can be realized by rewriting the operation mode register 230 by any master processor. After the change of the operation mode, the processor changed from the checker processor to the master processor operates independently of the instruction following the change of the operation mode. After the switching, each processor recognizes its own processor number and executes an independent program.

FIG. 10 shows an example of the internal logical configuration of the fault report control unit 266. This is because the comparators 270-270
275 and the comparators 276 to 281 compare the request signal from each processor with the logical processor number in all combinations, and through the NOT gates 290 to 295, the AND gates 300 to 305, and the OR gate, in the combinations in which the logical processor numbers match. When there is a request signal that does not match, a failure report signal 267 is output.

Next, referring to FIGS. 11 and 12, using a service processor for performing maintenance and diagnosis of the processor,
An embodiment will be described in which an initial test of each processor is performed at the time of reset such as system startup to check for the presence / absence of an operable / unable processor, and the operation mode is automatically set in the operation mode register via a diagnostic path.

FIG. 11 is an overall configuration diagram of the present embodiment. In this case, the processor 0 (IPO) 1 and the processor 1 in FIG.
A case where the (IPO) 2 is applied to a system configuration connected to a main storage control unit (SCU) 3 is shown. 11, the internal configuration of the SCU 3 is the same as that of FIG. 1, and includes an operation mode register 22. The service processor (SVP) 5 includes processors 1 and 2, a main storage control device 3,
It is a processor that performs maintenance and diagnosis of the main storage device 4 and is connected to each device by an independent maintenance and diagnosis path. In FIG. 11, the path between the service processor 5 and the main storage device 4 is omitted for convenience.

FIG. 12 shows a processing flow chart of the operation mode setting by the configuration of FIG. At the time of reset, the main memory control device 3 operates in the multiprocessor mode. Processor 0
And 1 independently execute a self test (initial test) under the control of the service processor 5 (step 100).
1). Then, it is determined whether a defect is found in the self test (step 1002). If found, the subsequent operation is stopped and the operation is stopped in an infinite loop (step 1002).
3) If you pass the self-test successfully,
The K flag is turned on (step 1004). The service processor 5 waits until the self-test OK flag of the other processor is turned on (steps 1005 and 1006).
When the self-test OK flag is turned on for both the devices (YES in step 1005), the configuration information instructed in advance is read (step 1007), and according to the information (step 1008), the operation mode register 22 of the SCU 3 is operated using the diagnostic path. Set the mode (step 101
0, 1012), and shift to normal processing. On the other hand, if the self-test OK flag of the other processor does not turn on after a certain period of time (YES in step 1006), it is determined that the other processor does not operate (step 10).
09), the service processor 5 sets the master checker mode in which the operable processor becomes the master processor (steps 1010 and 1011), and shifts to the normal processing.

When one of the processors 0 and 1 does not exist, the self-test O
Since the K flag is not turned on, the operating processor may be set as the master processor and the processing may be continued as in the case where a failure occurs in the self test. The configuration information can be prepared in advance as hardware components or can be given as a command from software, for example, from an operator console.

Further, although the service processor is used in FIG. 11, at the time of reset, the processors 0 and 1 independently execute the processing flow of FIG. 12 and operate mode register 2 by the register write request described above.
The second operation mode may be set. In this case, the self-test OK flag may be stored in a specific area of the main storage device 4, and the processors 0 and 1 may see it to determine whether or not the self-test OK flag of another processor is on. When both processors are normal, each processor sets the operation mode, but there is no problem because the contents are the same.

[0049]

According to the first aspect of the present invention, in the information processing apparatus having two processors, the identification mode is set according to the state of the system (ie, when the system is started up or when a failure occurs). By making a change, it is possible to freely select a dual processor system or a multiprocessor system.

According to the second aspect of the present invention, in an information processing apparatus having three or more processors, each processor is provided with a logical processor number and an identification mode of a master mode or a checker mode, and these can be freely changed. It is possible to select a dual processor, a multiprocessor, or an arbitrary system in which these are combined according to the state of the system, and it is possible to freely construct a system with optimum performance and reliability.

According to the third aspect of the present invention, the identification mode and / or the logical processor number can be easily switched and controlled from an arbitrary processor in the same manner as a normal hardware register write.

According to the fourth aspect of the present invention, when the system is started, it is possible to automatically construct a system having an appropriate combination of performance and reliability in accordance with the operability / inability of each processor. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing contents of an operation mode register of FIG. 1;

FIG. 3 is an explanatory diagram of an operation of a processor switching control unit in FIG. 1;

FIG. 4 is an internal logic diagram of a processor switching control unit of FIG. 1;

FIG. 5 is an internal logic diagram of the failure report control unit of FIG. 1;

FIG. 6 is a time chart for explaining the operation in the multiprocessor mode of FIG. 1;

FIG. 7 is a configuration diagram showing a second embodiment of the present invention.

FIG. 8 is an explanatory diagram showing contents of an operation mode register of FIG. 7;

FIG. 9 is an operation explanatory diagram of the processor switching control unit of FIG. 7;

FIG. 10 is an internal logic diagram of the fault report control unit of FIG. 7;

FIG. 11 is a configuration diagram showing a third embodiment of the present invention.

FIG. 12 is a processing flowchart of an operation mode setting in FIG. 11;

[Explanation of symbols]

 1, 2 processor 3 main storage control unit (SCU) 4 main storage device 5 service processor 13 operation mode switching logic unit 22 operation mode register 23 failure report control unit 24 processor switching control unit 107 reception switching signal 110 operation mode switching signal 200 to 203 Processor 204 Main storage control device 205 Main storage device 230 Operation mode register 231 Processor switching control unit 234 Operation mode switching logic unit 266 Failure report control unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-62641 (JP, A) JP-A-2-123455 (JP, A) JP-A-2-130666 (JP, A) JP-A-1- 224861 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (4)

(57) [Claims] An information processing apparatus having a main storage device and two processors connected to the main storage device via a main storage control device, wherein the main storage control device is a multi-processor. and the operation mode register which indicates that operating in processor mode or master checker mode, based on the content of the operation mode register, the multiprocessor mode, the alternately to the two processors
In a multi-processor system in which a request to the main storage device is permitted and the two processors execute independent programs, in a master checker mode, requests to the main storage device are simultaneously permitted to the two processors. An information processing apparatus, wherein the two processors have control means for switching to a dual processor system that executes the same program as one of a master processor and the other as a checker processor. 2. An information processing apparatus having a main storage device and three or more processors connected to the main storage device via a main storage control device, wherein the main storage control device has a logic corresponding to each processor. It has a processor number and an identification bit for master mode or checker mode. Each processor in master mode has an independent logical processor number, and the same processor for checker mode as any processor in master mode. An operation mode register having a logical processor number, and a master mode processor and a checker mode processor having the same logical processor number are set as a set of duplexed processors based on the contents of the operation mode register. Check mode with no processor in checker mode with processor number Each processor is a single processor, and the dual processor and the single processor are sequentially assigned to the main storage device.
The request is permitted, and each of the duplicated processors and each of the independent processors execute an independent program, and the master processor and the checker processor of the duplicated processor execute the same program. Control means for controlling a multiprocessor system configuration using a combination of a duplicated processor and an arbitrary number of single processors. 3. The information processing apparatus according to claim 1 , wherein said main storage control device has means for detecting a mode switching write request from a processor and rewriting contents of said operation mode register. Information processing device. 4. The information processing apparatus of the mounting according to claim 1 or 2 SL, the service processor to perform maintenance and diagnostic processor is provided, the presence or absence of the service operable / disable the processor to perform the initial testing of the processor by the processor Detected and according to the configuration information specified in advance,
An information processing apparatus, wherein the contents of the operation mode register are set using a diagnosis path.