JPH05274169A - Computer - Google Patents

Abstract

PURPOSE:To provide a computer which diagnoses the fault of a memory without stopping the steady processing, never performs a down load operation even if a system memory part undergoes the read and write operations for diagnosis of the memory fault, and can automatically restore the contents of the faulty memory. CONSTITUTION:A computer consists of a CPU part 1, a primary memory part 5a and a secondary memory 5b which simultaneously write the data given from the part 1 and output these data through one of both memories, a diagnostic processor 6 which alternately diagnoses the troubles of both memory parts 5a and 5b, a selector 7 which selects one of parts 5a and 5b to which the part 1 or the processor 6 is connected, and an external interface part 3 which inputs a signal to point one of both parts 5a and 5b that should be diagnosed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer capable of detecting a system memory failure, automatically disconnecting the failure memory, and continuing processing without stopping the CPU unit of the computer which is operating steadily.

[0002]

2. Description of the Related Art FIG. 18 is a block diagram of a conventional computer.
In the figure, 1 is a CPU unit, 2 is a system memory unit for downloading and storing data, 3 is an external interface unit, and 4 is an internal bus composed of an address bus, a data bus and control signals.

The conventional computer is configured as described above, and data is downloaded to the system memory unit 2 through the external interface unit 3 and is operating. In order to execute the memory failure diagnosis program, the processing program in the steady state is stopped and the memory failure diagnosis program is executed. At this time, since the system memory unit 2 is read and written for memory failure diagnosis, the data stored in the steady-state processing is rewritten. For this reason, after the memory failure diagnosis is completed, the data is again downloaded to the system memory unit 2. If an error occurs in the failure diagnosis, the memory must be repaired and the operation of the computer must be restarted.

[0004]

In the conventional computer as described above, it is necessary to suspend the steady process in order to execute the memory failure diagnosis program, and the memory contents are rewritten by the diagnosis, so that the memory failure diagnosis is performed. You will have to perform the data download again later. Further, there is a problem that the operation cannot be restarted when an error occurs in the failure diagnosis.

The present invention has been made to solve the above problems, and executes memory failure diagnosis without stopping the steady processing operation, and the system memory unit 2 is provided with a read and a write for the memory failure diagnosis. The object of the present invention is to obtain a computer that can automatically restore the contents of the memory that has been subjected to the failure diagnosis without downloading the data again after the failure diagnosis of the memory.

Further, according to the present invention, the failure detection and the memory failure diagnosis are executed without stopping the processing when the memory data is abnormal, and the memory failure diagnosis is performed even if the system memory unit 2 is read and written for the memory failure diagnosis. After that, the contents of the fault-diagnosed memory can be restored automatically without downloading data, and if the fault diagnosis shows that the memory has a fault, the faulty memory is automatically disconnected.
The purpose is to obtain a computer that can continue processing.

[0007]

A computer according to the present invention is a memory unit consisting of a master system and a slave system for simultaneously writing data in response to a data write request from a CPU unit and outputting from only one of them, the above-mentioned master system. And a diagnostic processor for alternately diagnosing a failure of a slave memory, a selector for selecting whether to connect either the CPU unit or the diagnostic processor to a master memory or a slave memory, the master memory, or And a diagnostic control signal generating means for outputting to the diagnostic processor a signal instructing whether to diagnose the slave memory.

Further, the computer according to the present invention, in response to a data write request from the CPU section, simultaneously writes data and outputs from only one of them, a memory section consisting of a main system and a slave system, the above-mentioned master system and slave system memories. , A selector for selecting whether to connect either the CPU unit or the diagnostic processor to the main memory or the sub memory, and outputs of the main and sub memories. A comparison circuit for comparing data is provided, and when the data does not match in the comparison circuit, the failure diagnosis of the memory is alternately executed by the diagnosis processor, and the failure memory is automatically separated.

[0009]

According to the present invention, the main system memory and the slave system memory can be alternately connected to the CPU section 1 or the diagnostic processor, so that the steady process is not stopped even during the fault diagnosis and the fault diagnosis is performed. Even if the data is not downloaded again later, the data in the memory after the failure diagnosis is automatically restored.

Further, according to the present invention, the comparison circuit automatically detects a failure of the memory data and activates the diagnostic processor, so that the main memory and the slave memory are controlled by the CP.
The selector is switched so that it can be alternately connected to the U unit 1 or the diagnostic processor. As a result, the memory failure diagnosis can be automatically executed when the memory data fails, and if the failure diagnosis shows that the memory has a failure, the processing is continued by disconnecting the failed memory with the selector. Acts like.

[0011]

【Example】

Example 1. FIG. 1 is a block diagram of a computer showing an embodiment of the present invention. In the figure, 1, 3 and 4 are the same as in the conventional example. Reference numerals 5a and 5b are main memories and slave memories that simultaneously store data output from the CPU unit 1 and output data from either one to the CPU unit 1 when a read request is issued from the CPU unit 1, and 6 is a main system memory. Diagnostic processor for diagnosing the memory 5a or the subordinate memory 5b, and 7a and 7b are CPUs
A selector for switching whether or not to connect the main memory 5a and the slave memory 5b to the unit 1, 8a is a failure diagnosis request and a diagnostic control signal for instructing whether to diagnose the main memory 5a or the slave memory 5b. is there. During steady processing, main memory 5a
Data is output to the CPU unit 1. Selectors 7a, 7
The switch b executes the switching operation based on the diagnostic control signal 8 from the external interface unit 3. Reference numeral 9 is a diagnostic data transfer bus between the main memory 5a and the slave memory 5b and the diagnostic processor 6. Note that FIG. 1 shows a state in which both the main memory 5a and the slave memory 5b are connected to the CPU section 1 by selectors 7a and 7b.

FIG. 2 is a block diagram of the computer which is diagnosing the slave memory 5b, and FIG. 3 is a block diagram of the computer which is diagnosing the master memory 5a.

FIG. 4 is a block diagram of the diagnostic processor 6. In the figure, 10 is an operation control circuit, 11 is an input / output circuit for inputting / outputting diagnostic data of the main system memory 5a and the sub system memory 5b, and 12 is a memory circuit for storing a program and data for memory failure diagnosis.

The operation of the computer of the present invention will be described below with reference to FIGS. 1, 2, 3 and 4. In the steady processing operation, the main memory 5a and the slave memory 5b are connected to the internal bus 4 by using the selectors 7a and 7b as shown in FIG. At this time, the data output from the CPU unit 1 is simultaneously stored in both the main memory 5a and the slave memory 5b. Therefore, the same data is always held in the contents of the master memory 5a and the slave memory 5b. Further, when a read request is issued from the CPU unit 1, only the data from the main system memory 5a is output to the CPU unit 1.

Next, the case where the diagnostic control signal 8a is generated from the external interface section 3 will be described. The diagnostic processor 6 which has received the diagnostic control signal 8a selects the selectors 7a and 7b as shown in FIG. 2 or 3 depending on the instruction content of either the diagnostic of the slave memory 5b or the diagnostic of the master memory 5a.
To switch. CPU unit 1 for diagnosis of the slave memory 5b
The data output by is output only to the main memory 5a. The diagnostic processor 6 executes the failure diagnosis program stored in the memory circuit 12, and in parallel with the operations of the CPU unit 1 and the main memory 5a, it becomes possible to execute the memory failure diagnosis of the slave memory 5b. ..

When the diagnosis of the slave memory 5b is completed, the diagnosis processor 6 switches the state of the selector 7b of FIG. 2 as shown in FIG. After this, the data from the CPU unit 1 is written to the master memory 5a and the slave memory 5b in the same manner as during the regular processing, and the contents of the slave memory 5b are automatically updated without external download as in the conventional case. I will be back.

Next, when the diagnosis of the main system memory 5a is requested, the diagnosis processor 6 switches the selectors 7a and 7b as shown in FIG. At this time, the output from the CPU unit 1 is the slave memory 5
Only written to b. Further, in response to a read request from the CPU unit 1, the data in the slave memory 5b is output to the internal bus 4. The diagnostic processor 6 enables the main memory 5a to be diagnosed in parallel with the operation of the CPU unit 1, similarly to the diagnosis of the subordinate memory 5b.

After the failure diagnosis of the main system memory 5a, the diagnostic processor 6 switches the selector 7a again as shown in FIG.
The output from the PU unit 1 is used as the main memory 5a and the slave memory 5
Return to the normal processing operation of writing in b.

Second Embodiment FIG. 5 is a configuration diagram of a computer showing a second embodiment of the present invention. In the figure, 13 is a programmable diagnosis request signal generation circuit for activating the diagnosis processor 6 at an arbitrary timing, and 8b is a failure control request and a diagnosis control signal for instructing whether to diagnose the main memory 5a or the slave memory 5b. .. During steady processing, the data in the main system memory 5a is output to the CPU unit 1. The selectors 7a and 7b execute the switching operation based on the diagnostic control signal 8b from the programmable diagnostic request signal generating circuit 13. Reference numeral 14 is diagnostic request timing data for setting the timing at which the diagnostic control signal 8b is generated. 5 shows the main memory 5a and the slave memory 5
Both b show a state in which they are connected to the CPU section 1 by selectors 7a and 7b.

FIG. 6 is a block diagram of the programmable diagnosis request signal generation circuit 13. In the figure, 15 is a read control circuit for inputting the diagnostic request timing data 14, and 16 is a counter for generating the diagnostic control signal 8b. Reference numeral 17 is a control register that stores information of the read control circuit 15 and controls the counter 16. The counter 16 generates a diagnosis control signal 8b according to the input diagnosis request timing data 14.

FIG. 7 is a block diagram of the computer during diagnosis of the slave memory 5b, and FIG. 8 is a block diagram of the computer during diagnosis of the master memory 5a.

FIG. 9 is a timing chart of the computer. In the figure, T1 is a state in which the CPU unit 1 is in a steady process. T2 is a state in which the diagnostic processor 6 is diagnosing the slave memory 5b, and T3 is a state in which the master memory 5a is being diagnosed. The states of the selectors 7a and 7b are set as shown in FIG. 1 during the periods T4, T5, and T6. The state of the selectors 7a and 7b during the period of T2 is as shown in FIG.
The states of a and 7b are set as shown in FIG.

The operation of the computer of the present invention will be described below with reference to FIGS. During the steady processing operation, as shown in FIG. 5, the main memory 5a and the slave memory 5b are connected to the internal bus 4 by using the selectors 7a and 7b. At this time, C
The data output from the PU unit 1 is simultaneously stored in both the main memory 5a and the slave memory 5b. Therefore, the same data is always held in the contents of the master memory 5a and the slave memory 5b. Further, when a read request is issued from the CPU unit 1, only the data from the main system memory 5a is sent to the CPU unit 1
Works to output to. This operating state corresponds to the T4, T5, and T6 periods in FIG.

The timing of the diagnostic request is set in the control register 17 and the counter 16 from the diagnostic request timing data 14 through the read control circuit 15 in the programmable diagnostic request signal generation circuit 13. Thereby, the diagnosis of the CPU unit 1 can be executed at any timing.

Next, the case where the diagnostic control signal 8b is generated from the programmable diagnostic request signal generating circuit 13 will be described. The diagnostic processor 6 receiving the diagnostic control signal 8b
The selectors 7a and 7b are switched as shown in FIG. 4 or 5 depending on the instruction content of either the diagnosis of the slave memory 5b or the diagnosis of the master memory 5a.

In the case of diagnosing the slave memory 5b, the selectors 7a and 7b are switched as shown in FIG. 7, and the data output by the CPU section 1 is output only to the master memory 5a. The diagnostic processor 6 executes the failure diagnostic program stored in the memory circuit 12 of FIG. 4, and the CPU unit 1 and the main system memory 5
In parallel with the operation of a, it becomes possible to execute the memory failure diagnosis of the slave memory 5b. This operating state corresponds to the T2 period in FIG.

When the diagnosis of the slave memory 5b is completed, the diagnosis processor 6 switches the state of the selector 7b of FIG. 7 as shown in FIG. After this, the data from the CPU unit 1 is written to the master memory 5a and the slave memory 5b in the same manner as during the regular processing, and the contents of the slave memory 5b are automatically updated without external download as in the conventional case. I will be back.

Next, when the diagnostic control signal 8b is generated from the programmable diagnostic request signal generating circuit 13, the diagnostic request of the main system memory 5a is issued, and the diagnostic processor 6 switches the selectors 7a and 7b as shown in FIG. At this time, CPU
The output from the section 1 is written only in the slave memory 5b.
Further, in response to a read request from the CPU unit 1, the data in the slave memory 5b is output to the internal bus 4.
The diagnostic processor 6 enables the main memory 5a to be diagnosed in parallel with the operation of the CPU unit 1, similarly to the diagnosis of the subordinate memory 5b. This operating state corresponds to the T3 period in FIG.

After the failure diagnosis of the main system memory 5a, the diagnostic processor 6 switches the selector 7a again as shown in FIG.
The output from the PU unit 1 is used as the main memory 5a and the slave memory 5
Return to the normal processing operation of writing in b.

As described above, in the second embodiment of the present invention, the CP
Simultaneous with the regular processing operation of the U unit 1, the failure diagnosis of the master memory 5a and the slave memory 5b can be executed at an arbitrary timing by an instruction from the outside. Further, even when the master memory 5a or the slave memory 5b rewritten by the read / write of the memory failure diagnosis is re-migrated to the steady processing operation, it is automatically rewritten to the steady data without downloading from the outside. Have.

Third Embodiment FIG. 10 is a configuration diagram of a computer showing a third embodiment of the present invention. In the figure, 18 is a diagnostic control timer for periodically activating the diagnostic processor, and 8c is a diagnostic control signal and a diagnostic control signal for instructing whether to diagnose the main memory 5a or the slave memory 5b. During steady processing, main memory 5a
Data is output to the CPU unit 1. Selectors 7a, 7
The switch b executes the switching operation based on the diagnostic control signal 9 from the diagnostic control timer 8.

FIG. 10 shows a state in which both the main memory 5a and the slave memory 5b are connected to the CPU section 1 by the selectors 7a and 7b. FIG. 11 is a block diagram of the computer during diagnosis of the slave memory 5b, and FIG. 12 is a block diagram of the computer during diagnosis of the main memory 5a.

FIG. 13 is a timing chart of the computer. In the figure, T1 is a state in which the CPU unit 1 is in a steady process. T2 is a state in which the diagnostic processor 6 is diagnosing the slave memory 5b, and T3 is a state in which the master memory 5a is being diagnosed. The states of the selectors 7a and 7b are set as shown in FIG. 10 during the periods T4, T5, and T6. It is shown that the states of the selectors 7a and 7b are set as shown in FIG. 11 during the period of T2, and the states of the selectors 7a and 7b are set as shown in FIG. 12 during the period of T3.

The operation of the computer of the present invention will be described below with reference to FIGS. 4 and 10 to 13. During the steady processing operation, as shown in FIG. 10, the main memory 5a and the slave memory 5 are
b is connected to the internal bus 4 by using the selectors 7a and 7b. At this time, the data output from the CPU unit 1 is simultaneously stored in both the main memory 5a and the slave memory 5b. Therefore, the same data is always held in the contents of the master memory 5a and the slave memory 5b. Further, when a read request is issued from the CPU unit 1, only the data from the main system memory 5a is output to the CPU unit 1. This operating state corresponds to the T4, T5, and T6 periods in FIG.

Next, the case where the diagnostic control signal 8c is generated from the diagnostic control timer 18 will be described. Diagnostic control signal 8
The diagnostic processor 6 which has received the command c, as shown in FIG. 11 or 12, selects the selectors 7a and 7b according to the instruction content of either the diagnosis of the slave memory 5b or the diagnosis of the master memory 5a.
To switch. CPU unit 1 for diagnosis of the slave memory 5b
The data output by is output only to the main memory 5a. The diagnostic processor 6 executes the failure diagnosis program stored in the memory circuit 12, and in parallel with the operations of the CPU unit 1 and the main memory 5a, it becomes possible to execute the memory failure diagnosis of the slave memory 5b. .. This operation state corresponds to the T2 period in FIG.

When the diagnosis of the slave memory 5b is completed, the diagnosis processor 6 switches the state of the selector 7b of FIG. 11 as shown in FIG. After this, the data from the CPU unit 1 is written to the master memory 5a and the slave memory 5b in the same manner as during the regular processing, and the contents of the slave memory 5b are automatically updated without external download as in the conventional case. I will be back.

Next, when the diagnostic control signal 8c is generated from the diagnostic control timer 18, a diagnostic request for the main system memory 5a is made, and the diagnostic processor 6 causes the selector 7 to operate as shown in FIG.
Switch a and 7b. At this time, the output from the CPU unit 1 is written only in the slave memory 5b. Also, the CPU unit 1
The data of the slave memory 5b is output to the internal bus 4 in response to the read request from the. Diagnostic processor 6
As a result, similarly to the diagnosis of the slave memory 5b,
It is possible to diagnose a in parallel with the operation of the CPU unit 1. This operating state corresponds to the T3 period in FIG.

After the failure diagnosis of the main system memory 5a, the diagnostic processor 6 switches the selector 7a again as shown in FIG.
The process returns to the regular processing operation of writing the output from the CPU unit 1 in the main memory 5a and the slave memory 5b.

Fourth Embodiment FIG. 14 is a configuration diagram of a computer showing a fourth embodiment of the present invention. In the figure, 1, 3, 4, 5a, 5b, 6, 7a,
7b and 9 are the same as in the above embodiment. Reference numeral 19 is a comparison circuit for comparing the output data to the CPU 1 of the main memory 5a and the sub memory 5b, and 8d is a failure control request and a diagnostic control signal for instructing whether to diagnose the main memory 5a or the sub memory 5b. Is. When the data in the master memory 5a and the data in the slave memory 5b match in the comparison circuit 19, the data in the master memory 5a is output to the CPU unit 1. Selectors 7a, 7b
Performs the switching operation based on the diagnostic control signal 8d from the CPU section 1.

Incidentally, FIG. 14 shows the operation in the normal state, in which both the main system memory 5a and the sub system memory 5b are provided in the CPU section 1 by the selector 7a,
7b shows a state of being connected by 7b. In addition, FIG.
Is a block diagram of a computer that is diagnosing the slave memory 5b, and FIG. 16 is a block diagram of a computer that is diagnosing the primary memory 5a.

FIG. 17 is a flow chart when the memory data of this computer is abnormal. Hereinafter, the operation of the computer of the present invention will be described with reference to FIGS. 4 and 14 to 17. During the steady processing operation, as shown in FIG. 14, the main memory 5a and the slave memory 5b are connected to the internal bus 4 by using the selectors 7a and 7b. At this time, the data output from the CPU unit 1 is simultaneously stored in both the main memory 5a and the slave memory 5b. Therefore, the same data is always held in the contents of the master memory 5a and the slave memory 5b. When a read request is issued from the CPU unit 1, the data of the main memory 5a and the slave memory 5b are compared by the comparison circuit 19 in step 20, and if the data match, only the data of the main memory 5a is output to the CPU unit 1. To work. If the data match, the memory failure diagnosis is not performed.

A case where the data in the master memory 5a and the data in the slave memory 5b do not match will be described. Step 20
If the data do not match, the CPU unit 1 outputs the diagnostic control signal 8d to the diagnostic processor 6. Step two
2 receives the diagnostic control signal 8d
First switches the selectors 7a and 7b as shown in FIG.
The slave memory 5b is diagnosed (step 23). In this state, the data output by the CPU unit 1 is the main memory 5
Only output to a. The diagnostic processor 6 is a memory circuit 1
Execute the failure diagnosis program stored in
In parallel with the operations of the U unit 1 and the master memory 5a, it becomes possible to execute the memory failure diagnosis of the slave memory 5b.

If it is found in step 24 that the slave memory 5b has a failure, the slave memory 5b is disconnected by continuing the processing while switching the selector state as shown in FIG. (Step 25). After disconnecting the slave memory 5b, the data from the CPU unit 1 is read / written only to the master memory 5a.

When the diagnosis of the slave memory 5b in step 24 reveals that the slave memory 5b has no failure, the diagnostic processor 6 next determines the state of the selector 7b of FIG.
Switch like 4. After that, the data from the CPU unit 1 is transferred to the main memory 5a and the slave memory 5 as in the steady processing.
The contents of the slave memory 5b are automatically restored without being downloaded from the outside as in the conventional case.

Next, the diagnostic CPU section 1 outputs the diagnostic control signal 8d to request the diagnostic of the main system memory 5a (step 2).
7). The diagnostic processor 6 has a selector 7 as shown in FIG.
Switching between a and 7b (step 26). At this time, CPU
The output from the section 1 is written only in the slave memory 5b.
Further, in response to a read request from the CPU unit 1, the data in the slave memory 5b is output to the internal bus 4.
The diagnostic processor 6 enables the main memory 5a to be diagnosed in parallel with the operation of the CPU unit 1, similarly to the diagnosis of the subordinate memory 5b.

After the failure diagnosis of the main memory 5a in step 28, when it is found that the main memory 5a has a failure, the processing is continued with the selector state switched as shown in FIG. The main system memory 5a is separated (step 29). After disconnecting the main memory 5a, the slave memory 5b
Only the data from the CPU unit 1 is read and written.

After the failure diagnosis of the main system memory 5a, if it is found that the main system memory 5a has no failure, the operation of the computer is stopped because it is considered to be a failure other than the memory (step 30).

[0048]

As described above, according to the present invention, CP
The failure diagnosis of the master memory 5a and the slave memory 5b can be executed at the same time as the steady processing operation of the U unit 1. In addition, the main system memory 5 rewritten by the read / write of the memory failure diagnosis
Even when "a" or the slave memory 5b is re-shifted to the steady processing operation, it has an effect of being automatically rewritten to the steady data without downloading from the outside.

Further, according to the present invention, when abnormality occurs in the memory data, the failure diagnosis of the main system memory 5a and the slave system memory 5b can be executed at the same time as the steady processing operation of the CPU section 1, and the failure memory is automatically executed. Disconnect. Further, the main system memory 5a rewritten by the read / write of the memory failure diagnosis
Alternatively, even when the slave memory 5b shifts to the steady processing operation again, it has an effect of being automatically rewritten to the steady data without downloading from the outside.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer according to a first embodiment of the present invention during a steady processing operation.

FIG. 2 is a configuration diagram of the computer according to the first embodiment of the present invention when diagnosing a slave memory failure.

FIG. 3 is a configuration diagram at the time of main system memory failure diagnosis of the computer according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of a diagnostic processor of a computer according to the present invention.

FIG. 5 is a configuration diagram of a computer according to a second embodiment of the present invention during a steady processing operation.

FIG. 6 is a configuration diagram of a programmable diagnostic request signal generating circuit of a computer according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a computer according to a second embodiment of the present invention when diagnosing a slave memory fault.

FIG. 8 is a configuration diagram at the time of main system memory failure diagnosis of a computer according to a second embodiment of the present invention.

FIG. 9 is a timing chart of the computer according to the second embodiment of the present invention.

FIG. 10 is a configuration diagram of a computer according to a third embodiment of the present invention during a steady processing operation.

FIG. 11 is a configuration diagram of a computer according to a third embodiment of the present invention when diagnosing a slave memory fault.

FIG. 12 is a configuration diagram at the time of main system memory failure diagnosis of a computer according to a third embodiment of the present invention.

FIG. 13 is a timing chart of the computer according to the third embodiment of the present invention.

FIG. 14 is a configuration diagram of a computer according to a fourth embodiment of the present invention during a steady processing operation.

FIG. 15 is a configuration diagram of a computer according to a fourth embodiment of the present invention when diagnosing a slave memory failure.

FIG. 16 is a configuration diagram at the time of main system memory failure diagnosis of a computer according to a fourth embodiment of the present invention.

FIG. 17 is a flowchart of a computer diagnosis according to the fourth embodiment of the present invention.

FIG. 18 is a block diagram of a conventional computer.

[Explanation of symbols]

 1 CPU part 2 System memory part 3 External interface part 5a Main memory 5b Slave memory 6 Diagnostic processor 7a Selector 7b Selector 8 Diagnostic control signal 9 Diagnostic data transfer bus 10 Arithmetic control circuit 11 Input / output circuit 12 Memory circuit 13 Programmable diagnostic request Signal generation circuit 15 Read control circuit 16 Counter 17 Control register 18 Diagnostic control timer 19 Comparison circuit

Claims (2)

[Claims] 1. A CPU unit, a memory unit consisting of a main system and a slave system which simultaneously write data in response to a data write request from this CPU unit and output from only one of them; A diagnostic processor for alternately diagnosing a failure, a selector for selecting whether to connect either the CPU unit or the diagnostic processor to the master memory or the slave memory, and to diagnose the master memory or the slave memory And a diagnostic control signal generating means for outputting a signal indicating that to the diagnostic processor. 2. A CPU section, a memory section consisting of a main system and a slave system which simultaneously write data in response to a data write request from this CPU section, and output from only one of them, and a memory of the main system and a slave system. Diagnostic processor for alternately diagnosing a failure, selector for selecting whether to connect either the CPU unit or the diagnostic processor to the master memory or the slave memory, output data of the master and slave memories When the data in the comparison circuit does not match, the memory fault diagnosis is alternately executed by the diagnostic processor to automatically disconnect the faulty memory. calculator.