JPS6218060B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a redundant system for a central processing unit (hereinafter abbreviated as "CPU") that is often used for control that requires high reliability, such as sequence control and direct control (DDC). It is also related to

As a conventional redundant system for this type of CPU,
There was something called a dual system in which a process input/output device (hereinafter abbreviated as "PIO") was accessed by two CPU systems. In other words, dual
Each CPU obtains the same common information from the PIO and executes calculations based on the same program, and the calculation results of both CPUs are checked at every arbitrary cycle block to see if they match each other. Process outputs based on calculation results were transferred as information.

However, since the conventional CPU redundancy system is as described above, there are hardware difficulties in sending and receiving PIO information to and from the CPUs of both systems, and access problems between the CPUs of both systems that operate on each other. It has a software difficulty in that it requires programmatic synchronization during execution.

Therefore, the present invention was made to solve the problems of the conventional ones as described above. As a CPU redundant system, control is usually performed by the operating CPU, and the standby CPU performs self-diagnosis etc. We use a redundant system that is always on standby to switch to the operating CPU and execute control based on commands.
First, on the condition that the information transfer path is normal so that the standby system can be switched to the operating system at any time,
The memory contents of the control system CPU are transferred to the memory of the standby system CPU in advance, and the image information of the process output is transferred to the PIO, and then the operating system CPU executes the program, after which it is checked whether the operating system CPU is normal or not. In the event of an error, the system switches to the standby system and executes the program again based on the transfer information in the memory of the standby CPU.
The purpose is to provide a redundant system that can easily perform bumpless backup.

Hereinafter, the present invention will be explained with reference to FIG. 1, which is a block diagram of the system, and FIG. 2, which is a control timing chart.
The diagram will be explained. In FIG. 1, reference numeral 2a denotes a first CPU which is an operating system CPU having a first memory 1a.
2b is a second CPU which is a standby CPU having a second memory 1b, and 3 is the first CPU 2.
A bus switching device with a simple configuration that controls switching between the active bus 5, the standby bus 6, and the input/output bus 7 in order to switch the execution process in the event of an abnormality, 4 is a physical and chemical state such as temperature and pressure; A process input/output unit (PIO) that converts information into electrical signals for processing by a CPU, and vice versa.

The operation of the redundant system shown in FIG. 1 will be explained for each timing shown in FIGS. 2A to 2D. First, during the period of the pulse width shown in FIG. A check is made to see if the path consisting of the control bus 5, bus switching device 3, standby bus 6, and second memory 1b is normal. This checking method includes a method of collecting an arbitrary pattern that is fixed or constantly changing every cycle from the first memory 1a, writing the pattern to the second memory 1b, and checking the pattern. Any method may be used in which an error detection code, such as parity, is generated at the same time, and the other party's memory (in this case, the second memory 1b) is checked through the error detection code.

If it is confirmed by this check that the above-mentioned information transfer path is normal, the bus switching device 3 transfers all data in the first memory 1a during the pulse width period shown in FIG. Information such as process output image information and calculation data as well as information such as a program counter, stack pointer, and status register necessary for controlling execution of the CPU is transferred to the second memory 1b. Furthermore, the image information of the process output among the information in the first memory 1a is transferred to the process input/output device 4. That is, due to these operations, the current execution result of the first CPU 2a is mapped to the outside (not shown) via the standby memory, in this case the second memory 1b and the PIO 4. be.

When this inter-memory information transfer is completed, the first CPU 2a executes the next stage of the program. The pulses in FIG. 2C indicate the duration of the run. In this case, the path between the PIO 4 and the first CPU 2a, that is, the path between the PIO 4, the input/output bus 7, the bus switching device 3, the driving bus 5, and the first CPU 2a processes process input in real time. Therefore, it is always open. That is, the first CPU 2a is accessed for the storage contents of the first memory 1a and the input information of the PIO 4.

When the first CPU 2a finishes executing one cycle of the program, the first CPU 2a
The CPU 2a itself is checked. The pulse width in FIG. 2D indicates this check period. This check may be performed by either a self-check by the first CPU 2a itself or an external check by the bus switching device 5.

However, by this check, the first
When it is determined that the CPU 2a is normal, the above-mentioned information transfer path is checked again, as shown by the second pulse in FIG. 2A. On the other hand, if an abnormality is found through this check, the standby CPU, that is,
Control is switched to the second CPU 2b. In this case, since the information of the previous cycle of the program, such as process output image information, etc., has already been transferred to the second memory 1b, the second CPU 2b re-starts the program based on this information. The execution of the cycle (the execution process performed by the first CPU 2a between the pulses in FIG. 2C) is carried out one by one. From this point on, the second CPU 2b constitutes the operating system, and the first CPU 2a constitutes the standby system, and performs the above-mentioned processing.

As described above, the present invention usually uses one of the two systems.
Using a redundant system in which one system is controlled by the CPU and the other system is on standby so that it can perform execution control in place of the operating CPU in the event of an abnormality, we first created an information transfer path so that the standby system could switch over to the operating system at any time. On the condition that the CPU is normal, the memory contents of the running CPU are transferred to the memory of the standby CPU in advance, and the image information of the process output is transferred to the PIO, and then the running CPU starts executing the program. After that, it is determined whether the running CPU is normal or not, and if there is an abnormality, it is switched to the standby system, and the standby CPU executes the program again, so the bumpless backup system can be converted into a simple hardware It has an excellent effect that it can be achieved by using a normal program format.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a redundant system according to the present invention, and FIGS. 2A to 2D are control timing charts of the redundant system according to the present invention. 1a, 1b: memory, 2a, 2b: CPU,
3: Bus switching device, 4: Process input/output device.

Claims (1)

[Claims] 1 The first controller inputs data from the process input/output device via the bus switching device to control execution.
It is equipped with an operating system consisting of a CPU and the memory of the CPU, and a standby system consisting of the memory of the CPU and a second CPU that stands by to perform execution control in place of the operating system in the event of an abnormality.Normally, the execution control is controlled by the operating system. In order to quickly switch to the standby system in the event of an abnormality, first,
The information transfer path from the memory of the first CPU to the memory of the second CPU via the bus switching device is diagnosed, and if it is normal, then the bus switching device
transfers all stored contents in the memory of the CPU to the memory of the second CPU, and also transfers process output image information among the information in the memory of the first CPU to the process input/output device; first
The CPU executes the program, and at the end of the execution,
Diagnose the first CPU itself, and if it is normal,
Proceeds to the next step, diagnostic processing of the information transfer path, and if it is found to be abnormal, execution control is switched to the standby system, and the second
Based on the transfer information in the memory of the CPU, the second
A central processing unit redundancy system, characterized in that the CPU achieves high reliability by running the aforementioned program again.