JPH0137769B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control processing device, and more particularly to a communication control processing device having an instruction retry function.

A communication control processing unit is usually provided between the line of an online communication device and a host central processing unit (CPU), and performs various processes such as processing of transmission control procedures. Communication control processing equipment is commonly provided for multiple lines, and if a failure occurs in the communication control processing equipment, all lines become unusable, so high reliability is required for communication control processing equipment. has been done. And for this reason, conventionally,
In order to improve reliability, devices were duplicated, and in the event of a failure, communication control was performed by switching to the other normal backup device.

By the way, some of the failures of communication control processing equipment include:
There are many systems that can operate normally if the command is retried, and it is not a good idea to switch between the active system and the standby system every time there is a simple and temporary failure like this.

The present invention is based on the above considerations, and aims to improve the reliability of a communication control processing device and reduce the number of switching operations during duplex operation. A communication control processing device that performs arithmetic processing includes a current address register indicating the address of the instruction currently being executed, an address register indicating the address of the next instruction to be executed, a retry control circuit, and a prefetch address register. A prefetch control circuit that controls prefetching, a buffer that stores the prefetched instruction, an instruction error latch that stores information that an error has occurred in an operation during execution of an instruction, and an instruction error latch that stores information that an error has occurred during instruction prefetching. It is provided with a prefetch error latch that stores the instruction prefetch, and performs instruction prefetch control, and also stores the above current state as the instruction retry address to be set in the prefetch address register based on the states of the instruction error latch and prefetch error latch when an error occurs. The present invention is characterized in that it is configured to determine which of the contents of the address register or the next address register is to be used.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an example of a communication control processing device based on the present invention, in which 1 is a main memory, 2 is an instruction register, 3 is an arithmetic circuit, 4 is an error detection circuit,
5 is a retry control circuit, 6 is a main memory address register, 7 is a next address register, 8 is a current address register, 9 is a step circuit, 10 and 11 are AND gates, 12 is an inversion gate, 13 is an OR gate, 14
is a deterrent gate, 15 is a retry start instruction signal line, 1
6 is an error detection signal line, and 17 is an inhibition instruction signal line. Note that one instruction consists of two bytes. During normal operation, the contents of the next address register are set in the main memory address register 6, read from the main memory 1, and the read instruction is set in the instruction register 2. At this time, the contents of the next address register are transferred to the current address register 8, and the value incremented by the increment circuit 9 is set in the next address register 7. The instruction set in the instruction register 2 is decoded and executed by the arithmetic circuit 3, and when the execution is completed normally, the next instruction is transferred to the instruction register 2 based on the contents of the next address register 7.
The data is read out and processed in the same way as above.

On the other hand, if an error occurs in the calculation result data of the calculation circuit 3, it is detected by the error detection circuit 4, and the error detection signal line 16 notifies the retry control circuit 5 of the error occurrence. As a result, the retry control circuit 5 uses the inhibition instruction signal line 17 to inhibit the arithmetic circuit 3 from performing an arithmetic operation regarding the next instruction, and to set the contents of the next address register 7 to the current address register 8. deter. Then, the AND gate 10 is controlled by the retry start instruction signal line 15, and the current address register 8 is
The contents of are set in the next address register 7. Furthermore, the contents of the next address register 7 are set in the main memory address register 6, and the contents are read from the main memory 1.
The instruction that caused the error is reread and set in the instruction register 2. As a result, the instruction is retried in the arithmetic circuit 3.

FIG. 2 is a time chart explaining the above operation. Next, FIG. 3 is a block diagram of a communication control processing device according to an embodiment of the present invention, in which the same numbers as in FIG. 1 have the same names, 19 is a prefetch buffer, and 20 is a prefetch address register. , 21
and 22 are AND gates, 23 are inversion gates, 24
is an OR gate, 25 is a retry start instruction signal line, 2
6 is a prefetch error latch for storing that an error has occurred during prefetching of an instruction; 27 is an instruction error latch for storing that an error has occurred in an operation during execution of an instruction; and 28 is an increment circuit. As in the example of FIG. 1, one instruction consists of two bytes.
The difference from the example shown in FIG. 1 is that an instruction prefetching function is added, and in addition to error detection during instruction execution, errors during instruction prefetching are also detected.

During normal operation, an operation is executed based on the contents of the instruction register 2, and the next instruction is read from the main memory 1 and set in the prefetch buffer 19. Each time an instruction is read, the contents of the prefetch address register 20 are transferred to the main memory address register 6, and the value incremented by the increment circuit 28 is set in the prefetch address register 20.

On the other hand, if an error occurs in the calculation result data of the calculation circuit 3, the error detection circuit 4
The instruction error latch 27 in the retry control circuit 5
Set. At this time, the same control as in the example shown in FIG. 1 is performed, and an instruction is read from main memory 1 based on the contents of current address register 8, which is not updated, and is set in instruction register 2. Thereafter, an instruction retry operation is performed.

Further, if an error occurs during prefetching of an instruction from main memory 1 to prefetch buffer 19, error detection circuit 4 sets prefetch error latch 26 in retry control circuit 5 via error detection signal line 16. At this time, by controlling the retry start instruction signal line 25,
Prefetch address register 20 by step circuit 28
The advance of the prefetch address register 20 is inhibited.
The contents of the next address register 7 are set. Then, based on the contents of the prefetch address register 20, a retry of prefetching the instruction from the main memory device 1 is performed, and the reread instruction is set in the prefetch buffer 19.

FIG. 4 is a time chart of the embodiment shown in FIG. 3, in which ERROR is a signal instructing error occurrence, Check-Reg is a register for setting error information, RQY1 and RQY2 are error signals, respectively.
RQ1M is the same as the instruction error latch 27 in FIG. 3, and RQ2M is the prefetch error latch 26 in FIG.
, IAR, LAR, SAR, and AAR are the same as the next address register 7, current address register 8, main memory address register 6, and prefetch address register 20 in FIG. 3, and SANT is the instruction read timing. SANC is the instruction execution timing, and IR is the same as instruction register 2. The time chart in FIG. 4 shows an example in which an error occurs simultaneously in both instruction execution and instruction prefetching, so a retry is made starting from fetching the instruction currently being executed.

As described above, according to the present invention, it is possible to retry the command, so it is possible to improve the reliability of the communication control processing device. (duplex) function, making it possible to make the data communication system more economical. Furthermore, even in the case of a duplex configuration, since the number of switching operations is reduced, it is possible to suppress a reduction in processing capacity.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a communication control processing device on which the present invention is based, FIG. 2 is a time chart of the example of FIG. 1, and FIG. 3 is a block diagram of a communication control processing device of an embodiment according to the present invention. 4 is a time chart of the embodiment of FIG. 3. In the figure, 1 is the main memory, 2 is the instruction register, and 3
is an arithmetic circuit, 4 is an error detection circuit, 5 is a retry control circuit, 6 is a main memory address register, 7 is a next address register, 8 is a current address register, 19 is a prefetch buffer, 20 is a prefetch address register, and 26 is a prefetch. Error latch 27 is an instruction error latch.

Claims (1)

[Claims] 1 In a communication control processing device that decodes instructions read from a storage device and performs arithmetic processing, there is a current address register indicating the address of the instruction currently being executed, a next address register indicating the address of the instruction to be executed next, and a retry register. a control circuit, a prefetch control circuit that includes a prefetch address register and controls prefetching of instructions, a prefetch buffer that stores the prefetched instructions, and an instruction error latch that stores information that an error has occurred in an operation during execution of an instruction. and a prefetch error latch that memorizes the occurrence of an error during prefetching of an instruction, and performs prefetch control of the instruction, and when an error occurs, the prefetch address register is set based on the state of the instruction error latch and the prefetch error latch. A communication control processing device, characterized in that it is configured to determine which of the contents of the current address register or the next address register is to be used as an instruction retry address to be set.