JPS5682940A - Communication controlling processor - Google Patents

Communication controlling processor

Info

Publication number
JPS5682940A
JPS5682940A JP16105379A JP16105379A JPS5682940A JP S5682940 A JPS5682940 A JP S5682940A JP 16105379 A JP16105379 A JP 16105379A JP 16105379 A JP16105379 A JP 16105379A JP S5682940 A JPS5682940 A JP S5682940A
Authority
JP
Japan
Prior art keywords
address register
circuit
error
arithmetic
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16105379A
Other languages
Japanese (ja)
Other versions
JPH0137769B2 (en
Inventor
Fumio Hoshi
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16105379A priority Critical patent/JPS5682940A/en
Publication of JPS5682940A publication Critical patent/JPS5682940A/en
Publication of JPH0137769B2 publication Critical patent/JPH0137769B2/ja
Granted legal-status Critical Current

Links

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  • Advance Control (AREA)
  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE: To improve reliability and to attain econonmization in a communication controlling processor having a retrying function, by setting the contents of a current- address register in a next-address register when an error is detected during the execution of arithmetic.
CONSTITUTION: An error, if occurring in the arithmetic result data of arithemtic circuit 3, is detected by error detecting circuit 4, and the error occurrence is informed to retry control circuit 5. Retry controlling circuit 5 stops the arithmetic operation of the next instruction by arithmetic circuit 3 and inhibits the contents of next-address register 7 from being set in current-address register 8. Through retry start indication signal line 15, AND gate 10 is controlled to set the contents of current-address register 8 in next-address register 7. Further, the contents of next-address register 7 are set in main-memory address register 6, the instruction having caused the error is read out of main memory device 1 again and arithmetic circuit 3 executes the instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP16105379A 1979-12-12 1979-12-12 Communication controlling processor Granted JPS5682940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16105379A JPS5682940A (en) 1979-12-12 1979-12-12 Communication controlling processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16105379A JPS5682940A (en) 1979-12-12 1979-12-12 Communication controlling processor

Publications (2)

Publication Number Publication Date
JPS5682940A true JPS5682940A (en) 1981-07-07
JPH0137769B2 JPH0137769B2 (en) 1989-08-09

Family

ID=15727706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16105379A Granted JPS5682940A (en) 1979-12-12 1979-12-12 Communication controlling processor

Country Status (1)

Country Link
JP (1) JPS5682940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218556A (en) * 1983-05-27 1984-12-08 Fujitsu Ltd Microprogram controlling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59218556A (en) * 1983-05-27 1984-12-08 Fujitsu Ltd Microprogram controlling system

Also Published As

Publication number Publication date
JPH0137769B2 (en) 1989-08-09

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